This appears optimal

Author: linuxrocks123

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

@@ -974,7 +974,9 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
                        Custom);
   }
 
-  setTargetDAGCombine({ISD::ADD,
+  setTargetDAGCombine({
+                       ISD::ABS,
+                       ISD::ADD,
                        ISD::PTRADD,
                        ISD::UADDO_CARRY,
                        ISD::SUB,
@@ -16854,6 +16856,11 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
   if (getTargetMachine().getOptLevel() == CodeGenOptLevel::None)
     return SDValue();
 
+  // expandABS but only for i8 and i16
+  if (N->getOpcode() == ISD::ABS && !N->isDivergent() &&
+      (N->getValueType(0) == MVT::i8 || N->getValueType(0) == MVT::i16))
+    return expandABS(N, DCI.DAG);
+
   switch (N->getOpcode()) {
   case ISD::ADD:
     return performAddCombine(N, DCI);