Skip to content

Commit 655709c

Browse files
arsenmarsenm
committed
RISCV: Enable terminal rule
1 parent b0f25b1 commit 655709c

File tree

8 files changed

+114
-120
lines changed

8 files changed

+114
-120
lines changed

‎llvm/lib/Target/RISCV/RISCVSubtarget.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -147,6 +147,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
147147
}
148148

149149
bool enableMachineScheduler() const override { return true; }
150+
bool enableTerminalRule() const override { return true; }
150151

151152
bool enablePostRAScheduler() const override { return UsePostRAScheduler; }
152153

‎llvm/test/CodeGen/RISCV/branch-on-zero.ll‎

Lines changed: 6 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -127,13 +127,11 @@ define i32 @test_lshr2(ptr nocapture %x, ptr nocapture readonly %y, i32 %n) {
127127
; RV32-NEXT: .LBB3_2: # %while.body
128128
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
129129
; RV32-NEXT: lw a3, 0(a1)
130-
; RV32-NEXT: addi a4, a1, 4
130+
; RV32-NEXT: addi a1, a1, 4
131131
; RV32-NEXT: slli a3, a3, 1
132-
; RV32-NEXT: addi a1, a0, 4
133132
; RV32-NEXT: sw a3, 0(a0)
134-
; RV32-NEXT: mv a0, a1
135-
; RV32-NEXT: mv a1, a4
136-
; RV32-NEXT: bne a4, a2, .LBB3_2
133+
; RV32-NEXT: addi a0, a0, 4
134+
; RV32-NEXT: bne a1, a2, .LBB3_2
137135
; RV32-NEXT: .LBB3_3: # %while.end
138136
; RV32-NEXT: li a0, 0
139137
; RV32-NEXT: ret
@@ -151,13 +149,11 @@ define i32 @test_lshr2(ptr nocapture %x, ptr nocapture readonly %y, i32 %n) {
151149
; RV64-NEXT: .LBB3_2: # %while.body
152150
; RV64-NEXT: # =>This Inner Loop Header: Depth=1
153151
; RV64-NEXT: lw a3, 0(a1)
154-
; RV64-NEXT: addi a4, a1, 4
152+
; RV64-NEXT: addi a1, a1, 4
155153
; RV64-NEXT: slli a3, a3, 1
156-
; RV64-NEXT: addi a1, a0, 4
157154
; RV64-NEXT: sw a3, 0(a0)
158-
; RV64-NEXT: mv a0, a1
159-
; RV64-NEXT: mv a1, a4
160-
; RV64-NEXT: bne a4, a2, .LBB3_2
155+
; RV64-NEXT: addi a0, a0, 4
156+
; RV64-NEXT: bne a1, a2, .LBB3_2
161157
; RV64-NEXT: .LBB3_3: # %while.end
162158
; RV64-NEXT: li a0, 0
163159
; RV64-NEXT: ret

‎llvm/test/CodeGen/RISCV/machine-pipeliner.ll‎

Lines changed: 23 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -54,37 +54,37 @@ define void @test_pipelined_1(ptr noalias %in, ptr noalias %out, i32 signext %cn
5454
; CHECK-PIPELINED: # %bb.0: # %entry
5555
; CHECK-PIPELINED-NEXT: blez a2, .LBB1_6
5656
; CHECK-PIPELINED-NEXT: # %bb.1: # %for.body.preheader
57-
; CHECK-PIPELINED-NEXT: lw a4, 0(a1)
57+
; CHECK-PIPELINED-NEXT: lw a7, 0(a1)
5858
; CHECK-PIPELINED-NEXT: addi a2, a2, -1
59+
; CHECK-PIPELINED-NEXT: addi a3, a0, 4
60+
; CHECK-PIPELINED-NEXT: addi a5, a1, 4
5961
; CHECK-PIPELINED-NEXT: sh2add.uw a6, a2, a1
60-
; CHECK-PIPELINED-NEXT: addi a2, a0, 4
61-
; CHECK-PIPELINED-NEXT: addi a1, a1, 4
6262
; CHECK-PIPELINED-NEXT: addi a6, a6, 4
63-
; CHECK-PIPELINED-NEXT: beq a1, a6, .LBB1_5
63+
; CHECK-PIPELINED-NEXT: beq a5, a6, .LBB1_5
6464
; CHECK-PIPELINED-NEXT: # %bb.2: # %for.body
65-
; CHECK-PIPELINED-NEXT: lw a5, 0(a1)
66-
; CHECK-PIPELINED-NEXT: addi a3, a2, 4
67-
; CHECK-PIPELINED-NEXT: addi a4, a4, 1
68-
; CHECK-PIPELINED-NEXT: addi a1, a1, 4
69-
; CHECK-PIPELINED-NEXT: beq a1, a6, .LBB1_4
65+
; CHECK-PIPELINED-NEXT: lw a1, 0(a5)
66+
; CHECK-PIPELINED-NEXT: addi a4, a3, 4
67+
; CHECK-PIPELINED-NEXT: addi a5, a5, 4
68+
; CHECK-PIPELINED-NEXT: beq a5, a6, .LBB1_4
7069
; CHECK-PIPELINED-NEXT: .LBB1_3: # %for.body
7170
; CHECK-PIPELINED-NEXT: # =>This Inner Loop Header: Depth=1
72-
; CHECK-PIPELINED-NEXT: sw a4, 0(a0)
73-
; CHECK-PIPELINED-NEXT: mv a4, a5
74-
; CHECK-PIPELINED-NEXT: lw a5, 0(a1)
75-
; CHECK-PIPELINED-NEXT: mv a0, a2
76-
; CHECK-PIPELINED-NEXT: mv a2, a3
77-
; CHECK-PIPELINED-NEXT: addi a3, a3, 4
78-
; CHECK-PIPELINED-NEXT: addi a4, a4, 1
79-
; CHECK-PIPELINED-NEXT: addi a1, a1, 4
80-
; CHECK-PIPELINED-NEXT: bne a1, a6, .LBB1_3
71+
; CHECK-PIPELINED-NEXT: addi a2, a7, 1
72+
; CHECK-PIPELINED-NEXT: mv a7, a1
73+
; CHECK-PIPELINED-NEXT: lw a1, 0(a5)
74+
; CHECK-PIPELINED-NEXT: sw a2, 0(a0)
75+
; CHECK-PIPELINED-NEXT: mv a0, a3
76+
; CHECK-PIPELINED-NEXT: mv a3, a4
77+
; CHECK-PIPELINED-NEXT: addi a4, a4, 4
78+
; CHECK-PIPELINED-NEXT: addi a5, a5, 4
79+
; CHECK-PIPELINED-NEXT: bne a5, a6, .LBB1_3
8180
; CHECK-PIPELINED-NEXT: .LBB1_4:
82-
; CHECK-PIPELINED-NEXT: sw a4, 0(a0)
83-
; CHECK-PIPELINED-NEXT: mv a0, a2
84-
; CHECK-PIPELINED-NEXT: mv a4, a5
81+
; CHECK-PIPELINED-NEXT: addi a7, a7, 1
82+
; CHECK-PIPELINED-NEXT: sw a7, 0(a0)
83+
; CHECK-PIPELINED-NEXT: mv a0, a3
84+
; CHECK-PIPELINED-NEXT: mv a7, a1
8585
; CHECK-PIPELINED-NEXT: .LBB1_5:
86-
; CHECK-PIPELINED-NEXT: addi a4, a4, 1
87-
; CHECK-PIPELINED-NEXT: sw a4, 0(a0)
86+
; CHECK-PIPELINED-NEXT: addi a7, a7, 1
87+
; CHECK-PIPELINED-NEXT: sw a7, 0(a0)
8888
; CHECK-PIPELINED-NEXT: .LBB1_6: # %for.end
8989
; CHECK-PIPELINED-NEXT: ret
9090
entry:

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll‎

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -44,9 +44,8 @@ define <4 x i64> @m2_splat_with_tail(<4 x i64> %v1) vscale_range(2,2) {
4444
; CHECK-LABEL: m2_splat_with_tail:
4545
; CHECK: # %bb.0:
4646
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
47-
; CHECK-NEXT: vrgather.vi v10, v8, 0
48-
; CHECK-NEXT: vmv1r.v v11, v9
49-
; CHECK-NEXT: vmv2r.v v8, v10
47+
; CHECK-NEXT: vmv1r.v v10, v8
48+
; CHECK-NEXT: vrgather.vi v8, v10, 0
5049
; CHECK-NEXT: ret
5150
%res = shufflevector <4 x i64> %v1, <4 x i64> poison, <4 x i32> <i32 0, i32 0, i32 2, i32 3>
5251
ret <4 x i64> %res
@@ -99,9 +98,8 @@ define <4 x i64> @m2_splat_into_identity(<4 x i64> %v1) vscale_range(2,2) {
9998
; CHECK-LABEL: m2_splat_into_identity:
10099
; CHECK: # %bb.0:
101100
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
102-
; CHECK-NEXT: vrgather.vi v10, v8, 0
103-
; CHECK-NEXT: vmv1r.v v11, v9
104-
; CHECK-NEXT: vmv2r.v v8, v10
101+
; CHECK-NEXT: vmv1r.v v10, v8
102+
; CHECK-NEXT: vrgather.vi v8, v10, 0
105103
; CHECK-NEXT: ret
106104
%res = shufflevector <4 x i64> %v1, <4 x i64> poison, <4 x i32> <i32 0, i32 0, i32 2, i32 3>
107105
ret <4 x i64> %res

‎llvm/test/CodeGen/RISCV/rvv/pr95865.ll‎

Lines changed: 21 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ define i32 @main(i1 %arg.1, i64 %arg.2, i1 %arg.3, i64 %arg.4, i1 %arg.5, <vscal
3636
; CHECK-NEXT: .cfi_offset s10, -96
3737
; CHECK-NEXT: .cfi_offset s11, -104
3838
; CHECK-NEXT: li a6, 0
39-
; CHECK-NEXT: li s2, 8
39+
; CHECK-NEXT: li a7, 8
4040
; CHECK-NEXT: li t0, 12
4141
; CHECK-NEXT: li s0, 4
4242
; CHECK-NEXT: li t1, 20
@@ -45,17 +45,17 @@ define i32 @main(i1 %arg.1, i64 %arg.2, i1 %arg.3, i64 %arg.4, i1 %arg.5, <vscal
4545
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
4646
; CHECK-NEXT: vmv.v.i v8, 0
4747
; CHECK-NEXT: andi t3, a4, 1
48-
; CHECK-NEXT: li t2, 4
48+
; CHECK-NEXT: li s2, 4
4949
; CHECK-NEXT: .LBB0_1: # %for.cond1.preheader.i
5050
; CHECK-NEXT: # =>This Loop Header: Depth=1
5151
; CHECK-NEXT: # Child Loop BB0_2 Depth 2
5252
; CHECK-NEXT: # Child Loop BB0_3 Depth 3
5353
; CHECK-NEXT: # Child Loop BB0_4 Depth 4
5454
; CHECK-NEXT: # Child Loop BB0_5 Depth 5
5555
; CHECK-NEXT: mv t4, t1
56-
; CHECK-NEXT: mv t5, t2
56+
; CHECK-NEXT: mv t2, s2
5757
; CHECK-NEXT: mv t6, t0
58-
; CHECK-NEXT: mv a7, s2
58+
; CHECK-NEXT: mv s3, a7
5959
; CHECK-NEXT: mv s4, a6
6060
; CHECK-NEXT: .LBB0_2: # %for.cond5.preheader.i
6161
; CHECK-NEXT: # Parent Loop BB0_1 Depth=1
@@ -64,9 +64,9 @@ define i32 @main(i1 %arg.1, i64 %arg.2, i1 %arg.3, i64 %arg.4, i1 %arg.5, <vscal
6464
; CHECK-NEXT: # Child Loop BB0_4 Depth 4
6565
; CHECK-NEXT: # Child Loop BB0_5 Depth 5
6666
; CHECK-NEXT: mv s5, t4
67-
; CHECK-NEXT: mv s6, t5
67+
; CHECK-NEXT: mv t5, t2
6868
; CHECK-NEXT: mv s7, t6
69-
; CHECK-NEXT: mv s3, a7
69+
; CHECK-NEXT: mv s8, s3
7070
; CHECK-NEXT: mv s9, s4
7171
; CHECK-NEXT: .LBB0_3: # %for.cond9.preheader.i
7272
; CHECK-NEXT: # Parent Loop BB0_1 Depth=1
@@ -75,9 +75,9 @@ define i32 @main(i1 %arg.1, i64 %arg.2, i1 %arg.3, i64 %arg.4, i1 %arg.5, <vscal
7575
; CHECK-NEXT: # Child Loop BB0_4 Depth 4
7676
; CHECK-NEXT: # Child Loop BB0_5 Depth 5
7777
; CHECK-NEXT: mv s11, s5
78-
; CHECK-NEXT: mv a3, s6
78+
; CHECK-NEXT: mv s6, t5
7979
; CHECK-NEXT: mv ra, s7
80-
; CHECK-NEXT: mv s8, s3
80+
; CHECK-NEXT: mv a5, s8
8181
; CHECK-NEXT: mv s1, s9
8282
; CHECK-NEXT: .LBB0_4: # %vector.ph.i
8383
; CHECK-NEXT: # Parent Loop BB0_1 Depth=1
@@ -92,45 +92,44 @@ define i32 @main(i1 %arg.1, i64 %arg.2, i1 %arg.3, i64 %arg.4, i1 %arg.5, <vscal
9292
; CHECK-NEXT: # Parent Loop BB0_3 Depth=3
9393
; CHECK-NEXT: # Parent Loop BB0_4 Depth=4
9494
; CHECK-NEXT: # => This Inner Loop Header: Depth=5
95-
; CHECK-NEXT: addi a5, a1, 4
96-
; CHECK-NEXT: add a4, s8, a1
97-
; CHECK-NEXT: add a1, a1, a3
95+
; CHECK-NEXT: add a4, a5, a1
96+
; CHECK-NEXT: add a3, s6, a1
97+
; CHECK-NEXT: addi a1, a1, 4
9898
; CHECK-NEXT: vse32.v v8, (a4), v0.t
99-
; CHECK-NEXT: vse32.v v8, (a1), v0.t
100-
; CHECK-NEXT: mv a1, a5
101-
; CHECK-NEXT: bne a5, s0, .LBB0_5
99+
; CHECK-NEXT: vse32.v v8, (a3), v0.t
100+
; CHECK-NEXT: bne a1, s0, .LBB0_5
102101
; CHECK-NEXT: # %bb.6: # %for.cond.cleanup15.i
103102
; CHECK-NEXT: # in Loop: Header=BB0_4 Depth=4
104103
; CHECK-NEXT: addi s1, s1, 4
105-
; CHECK-NEXT: addi s8, s8, 4
104+
; CHECK-NEXT: addi a5, a5, 4
106105
; CHECK-NEXT: addi ra, ra, 4
107-
; CHECK-NEXT: addi a3, a3, 4
106+
; CHECK-NEXT: addi s6, s6, 4
108107
; CHECK-NEXT: andi s10, a0, 1
109108
; CHECK-NEXT: addi s11, s11, 4
110109
; CHECK-NEXT: beqz s10, .LBB0_4
111110
; CHECK-NEXT: # %bb.7: # %for.cond.cleanup11.i
112111
; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=3
113112
; CHECK-NEXT: addi s9, s9, 4
114-
; CHECK-NEXT: addi s3, s3, 4
113+
; CHECK-NEXT: addi s8, s8, 4
115114
; CHECK-NEXT: addi s7, s7, 4
116-
; CHECK-NEXT: addi s6, s6, 4
115+
; CHECK-NEXT: addi t5, t5, 4
117116
; CHECK-NEXT: andi a1, a2, 1
118117
; CHECK-NEXT: addi s5, s5, 4
119118
; CHECK-NEXT: beqz a1, .LBB0_3
120119
; CHECK-NEXT: # %bb.8: # %for.cond.cleanup7.i
121120
; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=2
122121
; CHECK-NEXT: addi s4, s4, 4
123-
; CHECK-NEXT: addi a7, a7, 4
122+
; CHECK-NEXT: addi s3, s3, 4
124123
; CHECK-NEXT: addi t6, t6, 4
125-
; CHECK-NEXT: addi t5, t5, 4
124+
; CHECK-NEXT: addi t2, t2, 4
126125
; CHECK-NEXT: addi t4, t4, 4
127126
; CHECK-NEXT: beqz t3, .LBB0_2
128127
; CHECK-NEXT: # %bb.9: # %for.cond.cleanup3.i
129128
; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1
130129
; CHECK-NEXT: addi a6, a6, 4
131-
; CHECK-NEXT: addi s2, s2, 4
130+
; CHECK-NEXT: addi a7, a7, 4
132131
; CHECK-NEXT: addi t0, t0, 4
133-
; CHECK-NEXT: addi t2, t2, 4
132+
; CHECK-NEXT: addi s2, s2, 4
134133
; CHECK-NEXT: addi t1, t1, 4
135134
; CHECK-NEXT: beqz a1, .LBB0_1
136135
; CHECK-NEXT: # %bb.10: # %l.exit

‎llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll‎

Lines changed: 33 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -2258,18 +2258,18 @@ define void @vand_vx_loop_hoisted_not(ptr %a, i32 noundef signext %mask) {
22582258
; CHECK-RV32-NEXT: vsetvli a7, zero, e32, m2, ta, ma
22592259
; CHECK-RV32-NEXT: .LBB98_3: # %vector.body
22602260
; CHECK-RV32-NEXT: # =>This Inner Loop Header: Depth=1
2261-
; CHECK-RV32-NEXT: slli a7, a6, 2
2262-
; CHECK-RV32-NEXT: add t0, a6, a4
2263-
; CHECK-RV32-NEXT: add a7, a0, a7
2264-
; CHECK-RV32-NEXT: vl2re32.v v8, (a7)
2265-
; CHECK-RV32-NEXT: sltu a6, t0, a6
2266-
; CHECK-RV32-NEXT: add a5, a5, a6
2267-
; CHECK-RV32-NEXT: xor a6, t0, a3
2261+
; CHECK-RV32-NEXT: mv a7, a6
2262+
; CHECK-RV32-NEXT: slli t0, a6, 2
2263+
; CHECK-RV32-NEXT: add a6, a6, a4
2264+
; CHECK-RV32-NEXT: add t0, a0, t0
2265+
; CHECK-RV32-NEXT: vl2re32.v v8, (t0)
2266+
; CHECK-RV32-NEXT: sltu a7, a6, a7
2267+
; CHECK-RV32-NEXT: add a5, a5, a7
2268+
; CHECK-RV32-NEXT: xor a7, a6, a3
22682269
; CHECK-RV32-NEXT: vand.vx v8, v8, a1
2269-
; CHECK-RV32-NEXT: or t1, a6, a5
2270-
; CHECK-RV32-NEXT: vs2r.v v8, (a7)
2271-
; CHECK-RV32-NEXT: mv a6, t0
2272-
; CHECK-RV32-NEXT: bnez t1, .LBB98_3
2270+
; CHECK-RV32-NEXT: or a7, a7, a5
2271+
; CHECK-RV32-NEXT: vs2r.v v8, (t0)
2272+
; CHECK-RV32-NEXT: bnez a7, .LBB98_3
22732273
; CHECK-RV32-NEXT: # %bb.4: # %middle.block
22742274
; CHECK-RV32-NEXT: bnez a3, .LBB98_6
22752275
; CHECK-RV32-NEXT: .LBB98_5: # %for.body
@@ -2350,18 +2350,18 @@ define void @vand_vx_loop_hoisted_not(ptr %a, i32 noundef signext %mask) {
23502350
; CHECK-ZVKB-NOZBB32-NEXT: vsetvli a7, zero, e32, m2, ta, ma
23512351
; CHECK-ZVKB-NOZBB32-NEXT: .LBB98_3: # %vector.body
23522352
; CHECK-ZVKB-NOZBB32-NEXT: # =>This Inner Loop Header: Depth=1
2353-
; CHECK-ZVKB-NOZBB32-NEXT: slli a7, a6, 2
2354-
; CHECK-ZVKB-NOZBB32-NEXT: add t0, a6, a4
2355-
; CHECK-ZVKB-NOZBB32-NEXT: add a7, a0, a7
2356-
; CHECK-ZVKB-NOZBB32-NEXT: vl2re32.v v8, (a7)
2357-
; CHECK-ZVKB-NOZBB32-NEXT: sltu a6, t0, a6
2358-
; CHECK-ZVKB-NOZBB32-NEXT: add a5, a5, a6
2359-
; CHECK-ZVKB-NOZBB32-NEXT: xor a6, t0, a3
2353+
; CHECK-ZVKB-NOZBB32-NEXT: mv a7, a6
2354+
; CHECK-ZVKB-NOZBB32-NEXT: slli t0, a6, 2
2355+
; CHECK-ZVKB-NOZBB32-NEXT: add a6, a6, a4
2356+
; CHECK-ZVKB-NOZBB32-NEXT: add t0, a0, t0
2357+
; CHECK-ZVKB-NOZBB32-NEXT: vl2re32.v v8, (t0)
2358+
; CHECK-ZVKB-NOZBB32-NEXT: sltu a7, a6, a7
2359+
; CHECK-ZVKB-NOZBB32-NEXT: add a5, a5, a7
2360+
; CHECK-ZVKB-NOZBB32-NEXT: xor a7, a6, a3
23602361
; CHECK-ZVKB-NOZBB32-NEXT: vandn.vx v8, v8, a1
2361-
; CHECK-ZVKB-NOZBB32-NEXT: or t1, a6, a5
2362-
; CHECK-ZVKB-NOZBB32-NEXT: vs2r.v v8, (a7)
2363-
; CHECK-ZVKB-NOZBB32-NEXT: mv a6, t0
2364-
; CHECK-ZVKB-NOZBB32-NEXT: bnez t1, .LBB98_3
2362+
; CHECK-ZVKB-NOZBB32-NEXT: or a7, a7, a5
2363+
; CHECK-ZVKB-NOZBB32-NEXT: vs2r.v v8, (t0)
2364+
; CHECK-ZVKB-NOZBB32-NEXT: bnez a7, .LBB98_3
23652365
; CHECK-ZVKB-NOZBB32-NEXT: # %bb.4: # %middle.block
23662366
; CHECK-ZVKB-NOZBB32-NEXT: bnez a3, .LBB98_7
23672367
; CHECK-ZVKB-NOZBB32-NEXT: .LBB98_5: # %for.body.preheader
@@ -2444,18 +2444,18 @@ define void @vand_vx_loop_hoisted_not(ptr %a, i32 noundef signext %mask) {
24442444
; CHECK-ZVKB-ZBB32-NEXT: vsetvli a7, zero, e32, m2, ta, ma
24452445
; CHECK-ZVKB-ZBB32-NEXT: .LBB98_3: # %vector.body
24462446
; CHECK-ZVKB-ZBB32-NEXT: # =>This Inner Loop Header: Depth=1
2447-
; CHECK-ZVKB-ZBB32-NEXT: slli a7, a6, 2
2448-
; CHECK-ZVKB-ZBB32-NEXT: add t0, a6, a4
2449-
; CHECK-ZVKB-ZBB32-NEXT: add a7, a0, a7
2450-
; CHECK-ZVKB-ZBB32-NEXT: vl2re32.v v8, (a7)
2451-
; CHECK-ZVKB-ZBB32-NEXT: sltu a6, t0, a6
2452-
; CHECK-ZVKB-ZBB32-NEXT: add a5, a5, a6
2453-
; CHECK-ZVKB-ZBB32-NEXT: xor a6, t0, a3
2447+
; CHECK-ZVKB-ZBB32-NEXT: mv a7, a6
2448+
; CHECK-ZVKB-ZBB32-NEXT: slli t0, a6, 2
2449+
; CHECK-ZVKB-ZBB32-NEXT: add a6, a6, a4
2450+
; CHECK-ZVKB-ZBB32-NEXT: add t0, a0, t0
2451+
; CHECK-ZVKB-ZBB32-NEXT: vl2re32.v v8, (t0)
2452+
; CHECK-ZVKB-ZBB32-NEXT: sltu a7, a6, a7
2453+
; CHECK-ZVKB-ZBB32-NEXT: add a5, a5, a7
2454+
; CHECK-ZVKB-ZBB32-NEXT: xor a7, a6, a3
24542455
; CHECK-ZVKB-ZBB32-NEXT: vandn.vx v8, v8, a1
2455-
; CHECK-ZVKB-ZBB32-NEXT: or t1, a6, a5
2456-
; CHECK-ZVKB-ZBB32-NEXT: vs2r.v v8, (a7)
2457-
; CHECK-ZVKB-ZBB32-NEXT: mv a6, t0
2458-
; CHECK-ZVKB-ZBB32-NEXT: bnez t1, .LBB98_3
2456+
; CHECK-ZVKB-ZBB32-NEXT: or a7, a7, a5
2457+
; CHECK-ZVKB-ZBB32-NEXT: vs2r.v v8, (t0)
2458+
; CHECK-ZVKB-ZBB32-NEXT: bnez a7, .LBB98_3
24592459
; CHECK-ZVKB-ZBB32-NEXT: # %bb.4: # %middle.block
24602460
; CHECK-ZVKB-ZBB32-NEXT: bnez a3, .LBB98_6
24612461
; CHECK-ZVKB-ZBB32-NEXT: .LBB98_5: # %for.body

‎llvm/test/CodeGen/RISCV/rvv/vcpop-shl-zext-opt.ll‎

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -25,24 +25,24 @@ define dso_local void @test_store1(ptr nocapture noundef writeonly %dst, ptr noc
2525
; RV32-NEXT: li a6, 0
2626
; RV32-NEXT: .LBB0_4: # %vector.body
2727
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
28-
; RV32-NEXT: slli t0, a7, 2
29-
; RV32-NEXT: addi t1, a7, 8
30-
; RV32-NEXT: add t0, a1, t0
28+
; RV32-NEXT: mv t0, a7
29+
; RV32-NEXT: slli t1, a7, 2
30+
; RV32-NEXT: addi a7, a7, 8
31+
; RV32-NEXT: add t1, a1, t1
3132
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
32-
; RV32-NEXT: vle32.v v8, (t0)
33-
; RV32-NEXT: sltu a7, t1, a7
34-
; RV32-NEXT: xor t0, t1, a5
35-
; RV32-NEXT: add a6, a6, a7
33+
; RV32-NEXT: vle32.v v8, (t1)
34+
; RV32-NEXT: sltu t0, a7, t0
35+
; RV32-NEXT: xor t1, a7, a5
36+
; RV32-NEXT: add a6, a6, t0
3637
; RV32-NEXT: vmslt.vx v12, v8, a2
3738
; RV32-NEXT: vcompress.vm v10, v8, v12
38-
; RV32-NEXT: vcpop.m a7, v12
39-
; RV32-NEXT: vsetvli zero, a7, e32, m2, ta, ma
39+
; RV32-NEXT: vcpop.m t0, v12
40+
; RV32-NEXT: vsetvli zero, t0, e32, m2, ta, ma
4041
; RV32-NEXT: vse32.v v10, (a0)
41-
; RV32-NEXT: slli a7, a7, 2
42-
; RV32-NEXT: or t0, t0, a6
43-
; RV32-NEXT: add a0, a0, a7
44-
; RV32-NEXT: mv a7, t1
45-
; RV32-NEXT: bnez t0, .LBB0_4
42+
; RV32-NEXT: slli t0, t0, 2
43+
; RV32-NEXT: or t1, t1, a6
44+
; RV32-NEXT: add a0, a0, t0
45+
; RV32-NEXT: bnez t1, .LBB0_4
4646
; RV32-NEXT: # %bb.5: # %middle.block
4747
; RV32-NEXT: bne a5, a3, .LBB0_9
4848
; RV32-NEXT: .LBB0_6: # %for.cond.cleanup

0 commit comments

Comments
 (0)