Changed the patch to work only with Integer vector types

Author: himadhith

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

@@ -4576,10 +4576,17 @@ bool PPCDAGToDAGISel::trySETCC(SDNode *N) {
     // * for k != 0, change SETNE to SETUGT (k > 0)
     // * for 0 != k, change SETNE to SETULT (0 < k)
     if (CC == ISD::SETNE) {
+      EVT VT = LHS.getValueType();
+
+      // Only optimize for integer types (avoid FP completely)
+      bool IsIntegerType =
+          VT.isInteger() ||
+          (VT.isVector() && VT.getVectorElementType().isInteger());
+      if(IsIntegerType){
       if (ISD::isBuildVectorAllZeros(RHS.getNode()))
         CC = ISD::SETUGT;
       else if (ISD::isBuildVectorAllZeros(LHS.getNode()))
-        CC = ISD::SETULT;
+        CC = ISD::SETULT;}
     }
     EVT VecVT = LHS.getValueType();
     bool Swap, Negate;

llvm/test/CodeGen/PowerPC/recipest.ll

@@ -1034,7 +1034,7 @@ define <4 x float> @hoo3_fmf(<4 x float> %a) #1 {
 ; CHECK-P7-NEXT:    vmaddfp v5, v5, v0, v3
 ; CHECK-P7-NEXT:    vmaddfp v3, v5, v4, v3
 ; CHECK-P7-NEXT:    vxor v4, v4, v4
-; CHECK-P7-NEXT:    vcmpgefp v2, v4, v2
+; CHECK-P7-NEXT:    vcmpeqfp v2, v2, v4
 ; CHECK-P7-NEXT:    vnot v2, v2
 ; CHECK-P7-NEXT:    vand v2, v2, v3
 ; CHECK-P7-NEXT:    blr