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arsenmPravin Jagtap
arsenm
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Pravin Jagtap
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AMDGPU: MC support for v_cvt_scalef32_pk32_{bf|f}16_{bf|fp}6 of gfx950. (#117591)
Co-authored-by: Pravin Jagtap <[email protected]>
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‎llvm/lib/Target/AMDGPU/SIInstrInfo.td‎

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@@ -1697,6 +1697,7 @@ class getVALUDstForVT<ValueType VT, bit IsTrue16 = 0, bit IsVOP3Encoding = 0> {
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VOPDstOperand_t16Lo128),
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VOPDstOperand<VGPR_32>);
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RegisterOperand ret = !cond(!eq(VT.Size, 1024) : VOPDstOperand<VReg_1024>,
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!eq(VT.Size, 512) : VOPDstOperand<VReg_512>,
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!eq(VT.Size, 256) : VOPDstOperand<VReg_256>,
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!eq(VT.Size, 128) : VOPDstOperand<VReg_128>,
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!eq(VT.Size, 64) : VOPDstOperand<VReg_64>,

‎llvm/lib/Target/AMDGPU/VOP3Instructions.td‎

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@@ -966,6 +966,10 @@ let SubtargetPredicate = HasFP4ConversionScaleInsts, mayRaiseFPException = 0 in
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let SubtargetPredicate = HasFP6BF6ConversionScaleInsts, mayRaiseFPException = 0 in {
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defm V_CVT_SCALEF32_PK32_F32_FP6 : VOP3Inst<"v_cvt_scalef32_pk32_f32_fp6", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_V32F32_V6I32_F32>>;
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defm V_CVT_SCALEF32_PK32_F32_BF6 : VOP3Inst<"v_cvt_scalef32_pk32_f32_bf6", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_V32F32_V6I32_F32>>;
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defm V_CVT_SCALEF32_PK32_F16_FP6 : VOP3Inst<"v_cvt_scalef32_pk32_f16_fp6", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_V32F16_V6I32_F32>>;
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defm V_CVT_SCALEF32_PK32_BF16_FP6 : VOP3Inst<"v_cvt_scalef32_pk32_bf16_fp6", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_V32BF16_V6I32_F32>>;
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defm V_CVT_SCALEF32_PK32_F16_BF6 : VOP3Inst<"v_cvt_scalef32_pk32_f16_bf6", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_V32F16_V6I32_F32>>;
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defm V_CVT_SCALEF32_PK32_BF16_BF6 : VOP3Inst<"v_cvt_scalef32_pk32_bf16_bf6", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_V32BF16_V6I32_F32>>;
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}
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let SubtargetPredicate = isGFX10Plus in {
@@ -1915,4 +1919,8 @@ defm V_CVT_SCALEF32_PK_BF16_FP4 : VOP3OpSel_Real_gfx9 <0x251>;
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let OtherPredicates = [HasFP6BF6ConversionScaleInsts] in {
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defm V_CVT_SCALEF32_PK32_F32_FP6 : VOP3_Real_gfx9<0x256, "v_cvt_scalef32_pk32_f32_fp6">;
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defm V_CVT_SCALEF32_PK32_F32_BF6 : VOP3_Real_gfx9<0x257, "v_cvt_scalef32_pk32_f32_bf6">;
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defm V_CVT_SCALEF32_PK32_F16_FP6 : VOP3_Real_gfx9<0x260, "v_cvt_scalef32_pk32_f16_fp6">;
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defm V_CVT_SCALEF32_PK32_BF16_FP6 : VOP3_Real_gfx9<0x261, "v_cvt_scalef32_pk32_bf16_fp6">;
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defm V_CVT_SCALEF32_PK32_F16_BF6 : VOP3_Real_gfx9<0x262, "v_cvt_scalef32_pk32_f16_bf6">;
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defm V_CVT_SCALEF32_PK32_BF16_BF6 : VOP3_Real_gfx9<0x263, "v_cvt_scalef32_pk32_bf16_bf6">;
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}

‎llvm/test/MC/AMDGPU/gfx950_asm_features.s‎

Lines changed: 21 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -892,4 +892,24 @@ v_cvt_scalef32_pk32_f32_fp6 v[2:33], v[2:7], v6
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: v_cvt_scalef32_pk32_f32_bf6 v[2:33], v[2:7], v6 ; encoding: [0x02,0x00,0x57,0xd2,0x02,0x0d,0x02,0x00]
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v_cvt_scalef32_pk32_f32_bf6 v[2:33], v[2:7], v6
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v_cvt_scalef32_pk32_f32_bf6 v[2:33], v[2:7], v6
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: v_cvt_scalef32_pk32_bf16_bf6 v[10:25], v[20:25], v8 ; encoding: [0x0a,0x00,0x63,0xd2,0x14,0x11,0x02,0x00]
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v_cvt_scalef32_pk32_bf16_bf6 v[10:25], v[20:25], v8
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: v_cvt_scalef32_pk32_bf16_bf6 v[10:25], v[20:25], v8 ; encoding: [0x0a,0x00,0x63,0xd2,0x14,0x11,0x02,0x00]
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v_cvt_scalef32_pk32_bf16_bf6 v[10:25], v[20:25], v8
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: v_cvt_scalef32_pk32_f16_bf6 v[10:25], v[20:25], v8 ; encoding: [0x0a,0x00,0x62,0xd2,0x14,0x11,0x02,0x00]
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v_cvt_scalef32_pk32_f16_bf6 v[10:25], v[20:25], v8
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: v_cvt_scalef32_pk32_bf16_fp6 v[10:25], v[20:25], v8 ; encoding: [0x0a,0x00,0x61,0xd2,0x14,0x11,0x02,0x00]
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v_cvt_scalef32_pk32_bf16_fp6 v[10:25], v[20:25], v8
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: v_cvt_scalef32_pk32_f16_fp6 v[10:25], v[20:25], v8 ; encoding: [0x0a,0x00,0x60,0xd2,0x14,0x11,0x02,0x00]
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v_cvt_scalef32_pk32_f16_fp6 v[10:25], v[20:25], v8

‎llvm/test/MC/AMDGPU/gfx950_err.s‎

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Original file line numberDiff line numberDiff line change
@@ -149,3 +149,51 @@ v_cvt_scalef32_pk32_f32_bf6 v[2:33], v[2:7], v6 div:2
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// GFX950: :[[@LINE+1]]:{{[0-9]+}}: error: not a valid operand
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v_cvt_scalef32_pk32_f32_bf6 v[2:33], v[2:7], v6 clamp div:2
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// GFX950: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction
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v_cvt_scalef32_pk32_bf16_bf6 v[10:25], v[20:25], v8 clamp
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// GFX950: :[[@LINE+1]]:{{[0-9]+}}: error: not a valid operand
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v_cvt_scalef32_pk32_bf16_bf6 v[10:25], v[20:25], v8 mul:2
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// GFX950: :[[@LINE+1]]:{{[0-9]+}}: error: not a valid operand
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v_cvt_scalef32_pk32_bf16_bf6 v[10:25], v[20:25], v8 div:2
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// GFX950: :[[@LINE+1]]:{{[0-9]+}}: error: not a valid operand
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v_cvt_scalef32_pk32_bf16_bf6 v[10:25], v[20:25], v8 clamp div:2
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// GFX950: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction
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v_cvt_scalef32_pk32_f16_bf6 v[10:25], v[20:25], v8 clamp
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// GFX950: :[[@LINE+1]]:{{[0-9]+}}: error: not a valid operand
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v_cvt_scalef32_pk32_f16_bf6 v[10:25], v[20:25], v8 mul:2
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// GFX950: :[[@LINE+1]]:{{[0-9]+}}: error: not a valid operand
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v_cvt_scalef32_pk32_f16_bf6 v[10:25], v[20:25], v8 div:2
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// GFX950: :[[@LINE+1]]:{{[0-9]+}}: error: not a valid operand
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v_cvt_scalef32_pk32_f16_bf6 v[10:25], v[20:25], v8 clamp div:2
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// GFX950: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction
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v_cvt_scalef32_pk32_bf16_fp6 v[10:25], v[20:25], v8 clamp
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// GFX950: :[[@LINE+1]]:{{[0-9]+}}: error: not a valid operand
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v_cvt_scalef32_pk32_bf16_fp6 v[10:25], v[20:25], v8 mul:2
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// GFX950: :[[@LINE+1]]:{{[0-9]+}}: error: not a valid operand
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v_cvt_scalef32_pk32_bf16_fp6 v[10:25], v[20:25], v8 div:2
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// GFX950: :[[@LINE+1]]:{{[0-9]+}}: error: not a valid operand
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v_cvt_scalef32_pk32_bf16_fp6 v[10:25], v[20:25], v8 clamp div:2
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// GFX950: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction
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v_cvt_scalef32_pk32_f16_fp6 v[10:25], v[20:25], v8 clamp
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// GFX950: :[[@LINE+1]]:{{[0-9]+}}: error: not a valid operand
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v_cvt_scalef32_pk32_f16_fp6 v[10:25], v[20:25], v8 mul:2
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// GFX950: :[[@LINE+1]]:{{[0-9]+}}: error: not a valid operand
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v_cvt_scalef32_pk32_f16_fp6 v[10:25], v[20:25], v8 div:2
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// GFX950: :[[@LINE+1]]:{{[0-9]+}}: error: not a valid operand
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v_cvt_scalef32_pk32_f16_fp6 v[10:25], v[20:25], v8 clamp div:2

‎llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt‎

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Original file line numberDiff line numberDiff line change
@@ -617,3 +617,15 @@
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# GFX950: v_cvt_scalef32_pk32_f32_bf6 v[2:33], v[2:7], v6 ; encoding: [0x02,0x00,0x57,0xd2,0x02,0x0d,0x02,0x00]
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0x02,0x00,0x57,0xd2,0x02,0x0d,0x02,0x00
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# GFX950: v_cvt_scalef32_pk32_bf16_bf6 v[10:25], v[20:25], v8 ; encoding: [0x0a,0x00,0x63,0xd2,0x14,0x11,0x02,0x00]
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0x0a,0x00,0x63,0xd2,0x14,0x11,0x02,0x00
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# GFX950: v_cvt_scalef32_pk32_f16_bf6 v[10:25], v[20:25], v8 ; encoding: [0x0a,0x00,0x62,0xd2,0x14,0x11,0x02,0x00]
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0x0a,0x00,0x62,0xd2,0x14,0x11,0x02,0x00
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# GFX950: v_cvt_scalef32_pk32_bf16_fp6 v[10:25], v[20:25], v8 ; encoding: [0x0a,0x00,0x61,0xd2,0x14,0x11,0x02,0x00]
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0x0a,0x00,0x61,0xd2,0x14,0x11,0x02,0x00
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# GFX950: v_cvt_scalef32_pk32_f16_fp6 v[10:25], v[20:25], v8 ; encoding: [0x0a,0x00,0x60,0xd2,0x14,0x11,0x02,0x00]
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0x0a,0x00,0x60,0xd2,0x14,0x11,0x02,0x00

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