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Delete GCNScheduleDAGMILive::RegionsWithMinOcc
1 parent e3b79af commit 658f21f

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2 files changed

+12
-30
lines changed

2 files changed

+12
-30
lines changed

llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp

Lines changed: 12 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -941,11 +941,9 @@ void GCNScheduleDAGMILive::finalizeSchedule() {
941941
Pressure.resize(Regions.size());
942942
RegionsWithHighRP.resize(Regions.size());
943943
RegionsWithExcessRP.resize(Regions.size());
944-
RegionsWithMinOcc.resize(Regions.size());
945944
RegionsWithIGLPInstrs.resize(Regions.size());
946945
RegionsWithHighRP.reset();
947946
RegionsWithExcessRP.reset();
948-
RegionsWithMinOcc.reset();
949947
RegionsWithIGLPInstrs.reset();
950948

951949
runSchedStages();
@@ -1095,8 +1093,7 @@ bool PreRARematStage::initGCNSchedStage() {
10951093
// fixed if there is another pass after this pass.
10961094
assert(!S.hasNextStage());
10971095

1098-
if (!GCNSchedStage::initGCNSchedStage() || DAG.RegionsWithMinOcc.none() ||
1099-
DAG.Regions.size() == 1)
1096+
if (!GCNSchedStage::initGCNSchedStage() || DAG.Regions.size() == 1)
11001097
return false;
11011098

11021099
// Before performing any IR modification record the parent region of each MI
@@ -1138,11 +1135,6 @@ void UnclusteredHighRPStage::finalizeGCNSchedStage() {
11381135
SavedMutations.swap(DAG.Mutations);
11391136
S.SGPRLimitBias = S.VGPRLimitBias = 0;
11401137
if (DAG.MinOccupancy > InitialOccupancy) {
1141-
for (unsigned IDX = 0; IDX < DAG.Pressure.size(); ++IDX)
1142-
DAG.RegionsWithMinOcc[IDX] =
1143-
DAG.Pressure[IDX].getOccupancy(
1144-
DAG.ST, DAG.MFI.getDynamicVGPRBlockSize()) == DAG.MinOccupancy;
1145-
11461138
LLVM_DEBUG(dbgs() << StageID
11471139
<< " stage successfully increased occupancy to "
11481140
<< DAG.MinOccupancy << '\n');
@@ -1214,11 +1206,15 @@ bool GCNSchedStage::initGCNRegion() {
12141206
}
12151207

12161208
bool UnclusteredHighRPStage::initGCNRegion() {
1217-
// Only reschedule regions with the minimum occupancy or regions that may have
1218-
// spilling (excess register pressure).
1219-
if ((!DAG.RegionsWithMinOcc[RegionIdx] ||
1220-
DAG.MinOccupancy <= InitialOccupancy) &&
1221-
!DAG.RegionsWithExcessRP[RegionIdx])
1209+
// Only reschedule regions that have excess register pressure (i.e. spilling)
1210+
// or had minimum occupancy at the beginning of the stage (as long as
1211+
// rescheduling of previous regions did not make occupancy drop back down to
1212+
// the initial minimum).
1213+
unsigned DynamicVGPRBlockSize = DAG.MFI.getDynamicVGPRBlockSize();
1214+
if (!DAG.RegionsWithExcessRP[RegionIdx] &&
1215+
(DAG.MinOccupancy <= InitialOccupancy ||
1216+
DAG.Pressure[RegionIdx].getOccupancy(ST, DynamicVGPRBlockSize) !=
1217+
InitialOccupancy))
12221218
return false;
12231219

12241220
return GCNSchedStage::initGCNRegion();
@@ -1283,9 +1279,6 @@ void GCNSchedStage::checkScheduling() {
12831279
if (PressureAfter.getSGPRNum() <= S.SGPRCriticalLimit &&
12841280
PressureAfter.getVGPRNum(ST.hasGFX90AInsts()) <= S.VGPRCriticalLimit) {
12851281
DAG.Pressure[RegionIdx] = PressureAfter;
1286-
DAG.RegionsWithMinOcc[RegionIdx] =
1287-
PressureAfter.getOccupancy(ST, DynamicVGPRBlockSize) ==
1288-
DAG.MinOccupancy;
12891282

12901283
// Early out if we have achieved the occupancy target.
12911284
LLVM_DEBUG(dbgs() << "Pressure in desired limits, done.\n");
@@ -1319,7 +1312,6 @@ void GCNSchedStage::checkScheduling() {
13191312
if (NewOccupancy < DAG.MinOccupancy) {
13201313
DAG.MinOccupancy = NewOccupancy;
13211314
MFI.limitOccupancy(DAG.MinOccupancy);
1322-
DAG.RegionsWithMinOcc.reset();
13231315
LLVM_DEBUG(dbgs() << "Occupancy lowered for the function to "
13241316
<< DAG.MinOccupancy << ".\n");
13251317
}
@@ -1341,14 +1333,10 @@ void GCNSchedStage::checkScheduling() {
13411333

13421334
// Revert if this region's schedule would cause a drop in occupancy or
13431335
// spilling.
1344-
if (shouldRevertScheduling(WavesAfter)) {
1336+
if (shouldRevertScheduling(WavesAfter))
13451337
revertScheduling();
1346-
} else {
1338+
else
13471339
DAG.Pressure[RegionIdx] = PressureAfter;
1348-
DAG.RegionsWithMinOcc[RegionIdx] =
1349-
PressureAfter.getOccupancy(ST, DynamicVGPRBlockSize) ==
1350-
DAG.MinOccupancy;
1351-
}
13521340
}
13531341

13541342
unsigned
@@ -1578,9 +1566,6 @@ bool GCNSchedStage::mayCauseSpilling(unsigned WavesAfter) {
15781566
}
15791567

15801568
void GCNSchedStage::revertScheduling() {
1581-
DAG.RegionsWithMinOcc[RegionIdx] =
1582-
PressureBefore.getOccupancy(ST, DAG.MFI.getDynamicVGPRBlockSize()) ==
1583-
DAG.MinOccupancy;
15841569
LLVM_DEBUG(dbgs() << "Attempting to revert scheduling.\n");
15851570
DAG.RegionEnd = DAG.RegionBegin;
15861571
int SkippedDebugInstr = 0;

llvm/lib/Target/AMDGPU/GCNSchedStrategy.h

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -250,9 +250,6 @@ class GCNScheduleDAGMILive final : public ScheduleDAGMILive {
250250
// limit. Register pressure in these regions usually will result in spilling.
251251
BitVector RegionsWithExcessRP;
252252

253-
// Regions that has the same occupancy as the latest MinOccupancy
254-
BitVector RegionsWithMinOcc;
255-
256253
// Regions that have IGLP instructions (SCHED_GROUP_BARRIER or IGLP_OPT).
257254
BitVector RegionsWithIGLPInstrs;
258255

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