[AMDGPU][GlobalISel] Fix assert on APInt creation.

Since 3494ee9 APInt stopped
to implicitly truncate values, therefore it asserts
on a big signed value converted to (implicitly) unsigned APInt.

The change explicitly marks offset as a signed value.

Author: dfukalov

llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp

@@ -56,7 +56,7 @@ AMDGPU::getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg,
 
   Register Base;
   if (KnownBits && mi_match(Reg, MRI, m_GOr(m_Reg(Base), m_ICst(Offset))) &&
-      KnownBits->maskedValueIsZero(Base, APInt(32, Offset)))
+      KnownBits->maskedValueIsZero(Base, APInt(32, Offset, /*isSigned=*/true)))
     return std::pair(Base, Offset);
 
   // Handle G_PTRTOINT (G_PTR_ADD base, const) case

llvm/test/CodeGen/AMDGPU/GlobalISel/assert-signed-apint.ll

@@ -0,0 +1,14 @@
+; REQUIRES: asserts
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs -stop-after=instruction-select -o - %s | FileCheck %s
+
+; 
+
+; CHECK-LABEL: @test
+; CHECK: S_BUFFER_LOAD_DWORD_SGPR_IMM
+
+define amdgpu_cs void @test(<4 x i32> inreg %base, i32 inreg %i, ptr addrspace(1) inreg %out) {
+  %off = or i32 %i, -2147483648
+  %v = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %base, i32 %off, i32 0)
+  store i32 %v, ptr addrspace(1) %out, align 4
+  ret void
+}