Format the code

AmrDeveloper · AmrDeveloper · commit 65cb179daf17 · 2025-09-09T18:57:22.000+02:00
diff --git a/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp b/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
@@ -602,8 +602,7 @@ mlir::LogicalResult CIRToLLVMASinOpLowering::matchAndRewrite(
     cir::ASinOp op, OpAdaptor adaptor,
     mlir::ConversionPatternRewriter &rewriter) const {
   mlir::Type resTy = typeConverter->convertType(op.getType());
-  rewriter.replaceOpWithNewOp<mlir::LLVM::ASinOp>(op, resTy,
-                                                  adaptor.getSrc());
+  rewriter.replaceOpWithNewOp<mlir::LLVM::ASinOp>(op, resTy, adaptor.getSrc());
   return mlir::success();
 }
 

Original file line number	Diff line number	Diff line change
`@@ -602,8 +602,7 @@ mlir::LogicalResult CIRToLLVMASinOpLowering::matchAndRewrite(`
`602`	`602`	`cir::ASinOp op, OpAdaptor adaptor,`
`603`	`603`	`mlir::ConversionPatternRewriter &rewriter) const {`
`604`	`604`	`mlir::Type resTy = typeConverter->convertType(op.getType());`
`605`		`- rewriter.replaceOpWithNewOp<mlir::LLVM::ASinOp>(op, resTy,`
`606`		`- adaptor.getSrc());`
	`605`	`+ rewriter.replaceOpWithNewOp<mlir::LLVM::ASinOp>(op, resTy, adaptor.getSrc());`
`607`	`606`	`return mlir::success();`
`608`	`607`	`}`
`609`	`608`