[PowerPC][CodeGen] Use SETUEQ in copysign expansion

Author: workingjubilee

llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

@@ -1721,7 +1721,7 @@ void DAGTypeLegalizer::ExpandFloatRes_FCOPYSIGN(SDNode *N,
   // A double-double is Hi + Lo, so if Hi flips sign, so must Lo
   Lo = DAG.getSelectCC(DL, Tmp, Hi, Lo,
                        DAG.getNode(ISD::FNEG, DL, Lo.getValueType(), Lo),
-                       ISD::SETEQ);
+                       ISD::SETUEQ);
 }
 
 void DAGTypeLegalizer::ExpandFloatRes_FCOS(SDNode *N,

llvm/test/CodeGen/PowerPC/copysignl.ll

@@ -44,13 +44,13 @@ define ppc_fp128 @foo_ll(double %a, ppc_fp128 %b) #0 {
 ; CHECK-LABEL: foo_ll:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    fcpsgn 0, 2, 1
-; CHECK-NEXT:    li 3, 0
-; CHECK-NEXT:    li 4, 8
-; CHECK-NEXT:    fcmpu 0, 1, 0
-; CHECK-NEXT:    fmr 1, 0
-; CHECK-NEXT:    iseleq 3, 4, 3
+; CHECK-NEXT:    li 3, 8
 ; CHECK-NEXT:    addis 4, 2, .LCPI2_0@toc@ha
 ; CHECK-NEXT:    addi 4, 4, .LCPI2_0@toc@l
+; CHECK-NEXT:    fcmpu 0, 1, 0
+; CHECK-NEXT:    fmr 1, 0
+; CHECK-NEXT:    crnor 20, 2, 3
+; CHECK-NEXT:    isel 3, 0, 3, 20
 ; CHECK-NEXT:    lfdx 2, 4, 3
 ; CHECK-NEXT:    blr
 ;
@@ -59,8 +59,9 @@ define ppc_fp128 @foo_ll(double %a, ppc_fp128 %b) #0 {
 ; CHECK-VSX-NEXT:    fmr 0, 1
 ; CHECK-VSX-NEXT:    xscpsgndp 1, 2, 1
 ; CHECK-VSX-NEXT:    xxlxor 2, 2, 2
-; CHECK-VSX-NEXT:    xscmpudp 0, 0, 1
-; CHECK-VSX-NEXT:    beqlr 0
+; CHECK-VSX-NEXT:    fcmpu 0, 0, 1
+; CHECK-VSX-NEXT:    cror 20, 2, 3
+; CHECK-VSX-NEXT:    bclr 12, 20, 0
 ; CHECK-VSX-NEXT:  # %bb.1: # %entry
 ; CHECK-VSX-NEXT:    xsnegdp 2, 2
 ; CHECK-VSX-NEXT:    blr
@@ -74,13 +75,13 @@ define ppc_fp128 @foo_ld(double %a, double %b) #0 {
 ; CHECK-LABEL: foo_ld:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    fcpsgn 0, 2, 1
-; CHECK-NEXT:    li 3, 0
-; CHECK-NEXT:    li 4, 8
-; CHECK-NEXT:    fcmpu 0, 1, 0
-; CHECK-NEXT:    fmr 1, 0
-; CHECK-NEXT:    iseleq 3, 4, 3
+; CHECK-NEXT:    li 3, 8
 ; CHECK-NEXT:    addis 4, 2, .LCPI3_0@toc@ha
 ; CHECK-NEXT:    addi 4, 4, .LCPI3_0@toc@l
+; CHECK-NEXT:    fcmpu 0, 1, 0
+; CHECK-NEXT:    fmr 1, 0
+; CHECK-NEXT:    crnor 20, 2, 3
+; CHECK-NEXT:    isel 3, 0, 3, 20
 ; CHECK-NEXT:    lfdx 2, 4, 3
 ; CHECK-NEXT:    blr
 ;
@@ -89,8 +90,9 @@ define ppc_fp128 @foo_ld(double %a, double %b) #0 {
 ; CHECK-VSX-NEXT:    fmr 0, 1
 ; CHECK-VSX-NEXT:    xscpsgndp 1, 2, 1
 ; CHECK-VSX-NEXT:    xxlxor 2, 2, 2
-; CHECK-VSX-NEXT:    xscmpudp 0, 0, 1
-; CHECK-VSX-NEXT:    beqlr 0
+; CHECK-VSX-NEXT:    fcmpu 0, 0, 1
+; CHECK-VSX-NEXT:    cror 20, 2, 3
+; CHECK-VSX-NEXT:    bclr 12, 20, 0
 ; CHECK-VSX-NEXT:  # %bb.1: # %entry
 ; CHECK-VSX-NEXT:    xsnegdp 2, 2
 ; CHECK-VSX-NEXT:    blr
@@ -105,13 +107,13 @@ define ppc_fp128 @foo_lf(double %a, float %b) #0 {
 ; CHECK-LABEL: foo_lf:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    fcpsgn 0, 2, 1
-; CHECK-NEXT:    li 3, 0
-; CHECK-NEXT:    li 4, 8
-; CHECK-NEXT:    fcmpu 0, 1, 0
-; CHECK-NEXT:    fmr 1, 0
-; CHECK-NEXT:    iseleq 3, 4, 3
+; CHECK-NEXT:    li 3, 8
 ; CHECK-NEXT:    addis 4, 2, .LCPI4_0@toc@ha
 ; CHECK-NEXT:    addi 4, 4, .LCPI4_0@toc@l
+; CHECK-NEXT:    fcmpu 0, 1, 0
+; CHECK-NEXT:    fmr 1, 0
+; CHECK-NEXT:    crnor 20, 2, 3
+; CHECK-NEXT:    isel 3, 0, 3, 20
 ; CHECK-NEXT:    lfdx 2, 4, 3
 ; CHECK-NEXT:    blr
 ;
@@ -120,8 +122,9 @@ define ppc_fp128 @foo_lf(double %a, float %b) #0 {
 ; CHECK-VSX-NEXT:    fmr 0, 1
 ; CHECK-VSX-NEXT:    fcpsgn 1, 2, 1
 ; CHECK-VSX-NEXT:    xxlxor 2, 2, 2
-; CHECK-VSX-NEXT:    xscmpudp 0, 0, 1
-; CHECK-VSX-NEXT:    beqlr 0
+; CHECK-VSX-NEXT:    fcmpu 0, 0, 1
+; CHECK-VSX-NEXT:    cror 20, 2, 3
+; CHECK-VSX-NEXT:    bclr 12, 20, 0
 ; CHECK-VSX-NEXT:  # %bb.1: # %entry
 ; CHECK-VSX-NEXT:    xsnegdp 2, 2
 ; CHECK-VSX-NEXT:    blr

llvm/test/CodeGen/PowerPC/ctrloop-cpsgn.ll

@@ -57,8 +57,9 @@ define ppc_fp128 @foo(ptr nocapture %n, ppc_fp128 %d) nounwind readonly {
 ; CHECK-NEXT:  .LBB0_5: # %for.body
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    fcmpu 0, 2, 3
+; CHECK-NEXT:    cror 20, 2, 3
 ; CHECK-NEXT:    stfd 3, 56(1)
-; CHECK-NEXT:    beq 0, .LBB0_1
+; CHECK-NEXT:    bc 12, 20, .LBB0_1
 ; CHECK-NEXT:  # %bb.6: # %for.body
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    fneg 1, 1

llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll

@@ -92,20 +92,22 @@ define i128 @test_copysign(ppc_fp128 %x, ppc_fp128 %y) nounwind  {
 ; PPC64-P8-LABEL: test_copysign:
 ; PPC64-P8:       # %bb.0: # %entry
 ; PPC64-P8-NEXT:    xscpsgndp 0, 3, 1
-; PPC64-P8-NEXT:    xscmpudp 0, 1, 0
-; PPC64-P8-NEXT:    beq 0, .LBB2_2
+; PPC64-P8-NEXT:    fcmpu 0, 1, 0
+; PPC64-P8-NEXT:    cror 20, 2, 3
+; PPC64-P8-NEXT:    bc 12, 20, .LBB2_2
 ; PPC64-P8-NEXT:  # %bb.1: # %entry
 ; PPC64-P8-NEXT:    xsnegdp 2, 2
 ; PPC64-P8-NEXT:  .LBB2_2: # %entry
-; PPC64-P8-NEXT:    mffprd 3, 0
 ; PPC64-P8-NEXT:    mffprd 4, 2
+; PPC64-P8-NEXT:    mffprd 3, 0
 ; PPC64-P8-NEXT:    blr
 ;
 ; PPC64-LABEL: test_copysign:
 ; PPC64:       # %bb.0: # %entry
 ; PPC64-NEXT:    xscpsgndp 0, 3, 1
-; PPC64-NEXT:    xscmpudp 0, 1, 0
-; PPC64-NEXT:    beq 0, .LBB2_2
+; PPC64-NEXT:    fcmpu 0, 1, 0
+; PPC64-NEXT:    cror 20, 2, 3
+; PPC64-NEXT:    bc 12, 20, .LBB2_2
 ; PPC64-NEXT:  # %bb.1: # %entry
 ; PPC64-NEXT:    xsnegdp 2, 2
 ; PPC64-NEXT:  .LBB2_2: # %entry
@@ -125,16 +127,16 @@ define i128 @test_copysign(ppc_fp128 %x, ppc_fp128 %y) nounwind  {
 ; PPC32-NEXT:    bc 12, 1, .LBB2_2
 ; PPC32-NEXT:  # %bb.1: # %entry
 ; PPC32-NEXT:    fabs 0, 1
-; PPC32-NEXT:    fcmpu 0, 1, 0
-; PPC32-NEXT:    bne 0, .LBB2_3
-; PPC32-NEXT:    b .LBB2_4
+; PPC32-NEXT:    b .LBB2_3
 ; PPC32-NEXT:  .LBB2_2:
 ; PPC32-NEXT:    fnabs 0, 1
-; PPC32-NEXT:    fcmpu 0, 1, 0
-; PPC32-NEXT:    beq 0, .LBB2_4
 ; PPC32-NEXT:  .LBB2_3: # %entry
+; PPC32-NEXT:    fcmpu 0, 1, 0
+; PPC32-NEXT:    cror 20, 2, 3
+; PPC32-NEXT:    bc 12, 20, .LBB2_5
+; PPC32-NEXT:  # %bb.4: # %entry
 ; PPC32-NEXT:    fneg 2, 2
-; PPC32-NEXT:  .LBB2_4: # %entry
+; PPC32-NEXT:  .LBB2_5: # %entry
 ; PPC32-NEXT:    stfd 0, 24(1)
 ; PPC32-NEXT:    stfd 2, 16(1)
 ; PPC32-NEXT:    lwz 3, 24(1)