fixup! Remove unneed pattern now that tblgen can import sext_inreg

Author: topperc

llvm/lib/Target/RISCV/RISCVGISel.td

@@ -170,9 +170,6 @@ def : StPat<store, SD, GPR, PtrVT>;
 }
 
 let Predicates = [IsRV64] in {
-// FIXME: tblgen can't import sext_inreg patterns.
-def : Pat<(sra (sexti32 (i64 GPR:$rs1)), uimm5:$shamt),
-          (SRAIW GPR:$rs1, uimm5:$shamt)>;
 // FIXME: Temporary until i32->i64 zext is no longer legal.
 def : Pat <(srl (zext GPR:$rs1), uimm5:$shamt),
            (SRLIW GPR:$rs1, uimm5:$shamt)>;

llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll

@@ -454,7 +454,7 @@ define i8 @srai_i8(i8 %a) nounwind {
 ; RV64ZBB-LABEL: srai_i8:
 ; RV64ZBB:       # %bb.0:
 ; RV64ZBB-NEXT:    sext.b a0, a0
-; RV64ZBB-NEXT:    sraiw a0, a0, 5
+; RV64ZBB-NEXT:    srai a0, a0, 5
 ; RV64ZBB-NEXT:    ret
 ;
 ; RV64ZBKB-LABEL: srai_i8:
@@ -496,7 +496,7 @@ define i16 @srai_i16(i16 %a) nounwind {
 ; RV64ZBB-LABEL: srai_i16:
 ; RV64ZBB:       # %bb.0:
 ; RV64ZBB-NEXT:    sext.h a0, a0
-; RV64ZBB-NEXT:    sraiw a0, a0, 9
+; RV64ZBB-NEXT:    srai a0, a0, 9
 ; RV64ZBB-NEXT:    ret
 ;
 ; RV64ZBKB-LABEL: srai_i16:

llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll

@@ -1113,12 +1113,14 @@ define i32 @abs_i32(i32 %x) {
   ret i32 %abs
 }
 
+; FIXME: sext.w is not needed
 define signext i32 @abs_i32_sext(i32 signext %x) {
 ; RV64I-LABEL: abs_i32_sext:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    sraiw a1, a0, 31
-; RV64I-NEXT:    addw a0, a0, a1
+; RV64I-NEXT:    srai a1, a0, 31
+; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: abs_i32_sext: