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[RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple) extension (#119823)
This extension adds 6 instructions that can do multi-word load/store. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support.
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‎clang/test/Driver/print-supported-extensions-riscv.c‎

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@@ -191,6 +191,7 @@
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// CHECK-NEXT: xqcia 0.2 'Xqcia' (Qualcomm uC Arithmetic Extension)
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// CHECK-NEXT: xqcics 0.2 'Xqcics' (Qualcomm uC Conditional Select Extension)
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// CHECK-NEXT: xqcicsr 0.2 'Xqcicsr' (Qualcomm uC CSR Extension)
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// CHECK-NEXT: xqcilsm 0.2 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)
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// CHECK-NEXT: xqcisls 0.2 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
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// CHECK-EMPTY:
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// CHECK-NEXT: Supported Profiles

‎llvm/docs/RISCVUsage.rst‎

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@@ -435,6 +435,9 @@ The current vendor extensions supported are:
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``experimental-Xqcicsr``
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LLVM implements `version 0.2 of the Qualcomm uC CSR extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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``experimental-Xqcilsm``
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LLVM implements `version 0.2 of the Qualcomm uC Load Store Multiple extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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``experimental-Xqcisls``
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LLVM implements `version 0.2 of the Qualcomm uC Scaled Load Store extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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‎llvm/docs/ReleaseNotes.md‎

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@@ -223,6 +223,8 @@ Changes to the RISC-V Backend
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extension.
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* Adds experimental assembler support for the Qualcomm uC 'Xqcics` (Conditonal Select)
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extension.
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* Adds experimental assembler support for the Qualcomm uC 'Xqcilsm` (Load Store Multiple)
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extension.
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Changes to the WebAssembly Backend
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----------------------------------

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp‎

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@@ -724,6 +724,16 @@ struct RISCVOperand final : public MCParsedAsmOperand {
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bool isUImm48() const { return IsUImm<48>(); }
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bool isUImm64() const { return IsUImm<64>(); }
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bool isUImm5NonZero() const {
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if (!isImm())
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return false;
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int64_t Imm;
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RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
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bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
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return IsConstantImm && isUInt<5>(Imm) && (Imm != 0) &&
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VK == RISCVMCExpr::VK_RISCV_None;
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}
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bool isUImm8GE32() const {
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int64_t Imm;
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RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
@@ -1506,6 +1516,8 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 4) - 1);
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case Match_InvalidUImm5:
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return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 5) - 1);
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case Match_InvalidUImm5NonZero:
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return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 5) - 1);
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case Match_InvalidUImm6:
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return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 6) - 1);
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case Match_InvalidUImm7:

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp‎

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@@ -690,6 +690,8 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
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"Qualcomm uC Arithmetic custom opcode table");
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TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcics, DecoderTableXqcics32,
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"Qualcomm uC Conditional Select custom opcode table");
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TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcilsm, DecoderTableXqcilsm32,
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"Qualcomm uC Load Store Multiple custom opcode table");
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TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table");
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return MCDisassembler::Fail;

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h‎

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@@ -301,6 +301,7 @@ enum OperandType : unsigned {
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OPERAND_UIMM3,
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OPERAND_UIMM4,
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OPERAND_UIMM5,
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OPERAND_UIMM5_NONZERO,
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OPERAND_UIMM5_LSB0,
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OPERAND_UIMM6,
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OPERAND_UIMM6_LSB0,

‎llvm/lib/Target/RISCV/RISCVFeatures.td‎

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@@ -1375,6 +1375,14 @@ def HasVendorXqcics
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AssemblerPredicate<(all_of FeatureVendorXqcics),
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"'Xqcics' (Qualcomm uC Conditional Select Extension)">;
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def FeatureVendorXqcilsm
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: RISCVExperimentalExtension<"xqcilsm", 0, 2,
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"'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)">;
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def HasVendorXqcilsm
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: Predicate<"Subtarget->hasVendorXqcilsm()">,
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AssemblerPredicate<(all_of FeatureVendorXqcilsm),
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"'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)">;
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//===----------------------------------------------------------------------===//
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// LLVM specific features and extensions
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//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td‎

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@@ -14,6 +14,13 @@
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// Operand and SDNode transformation definitions.
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//===----------------------------------------------------------------------===//
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def uimm5nonzero : RISCVOp<XLenVT>,
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ImmLeaf<XLenVT, [{return (Imm != 0) && isUInt<5>(Imm);}]> {
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let ParserMatchClass = UImmAsmOperand<5, "NonZero">;
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let DecoderMethod = "decodeUImmNonZeroOperand<5>";
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let OperandType = "OPERAND_UIMM5_NONZERO";
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}
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def uimm11 : RISCVUImmLeafOp<11>;
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//===----------------------------------------------------------------------===//
@@ -105,6 +112,26 @@ class QCISELECTICCI<bits<3> funct3, string opcodestr>
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let rs1 = imm;
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}
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let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
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class QCILoadMultiple<bits<2> funct2, DAGOperand InTyRs2, string opcodestr>
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: RVInstRBase<0b111, OPC_CUSTOM_0, (outs GPRNoX0:$rd),
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(ins GPR:$rs1, InTyRs2:$rs2, uimm7_lsb00:$imm),
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opcodestr, "$rd, $rs2, ${imm}(${rs1})"> {
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bits<7> imm;
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let Inst{31-25} = {funct2, imm{6-2}};
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}
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// rd corresponds to the source for the store 'rs3' described in the spec.
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let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
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class QCIStoreMultiple<bits<2> funct2, DAGOperand InTyRs2, string opcodestr>
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: RVInstRBase<0b111, OPC_CUSTOM_1, (outs),
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(ins GPR:$rd, GPR:$rs1, InTyRs2:$rs2, uimm7_lsb00:$imm),
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opcodestr, "$rd, $rs2, ${imm}(${rs1})"> {
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bits<7> imm;
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let Inst{31-25} = {funct2, imm{6-2}};
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}
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
@@ -167,3 +194,34 @@ let Predicates = [HasVendorXqcics, IsRV32], DecoderNamespace = "Xqcics" in {
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def QC_SELECTIEQI : QCISELECTICCI <0b010, "qc.selectieqi">;
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def QC_SELECTINEI : QCISELECTICCI <0b011, "qc.selectinei">;
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} // Predicates = [HasVendorXqcics, IsRV32], DecoderNamespace = "Xqcics"
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let Predicates = [HasVendorXqcilsm, IsRV32], DecoderNamespace = "Xqcilsm" in {
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def QC_SWM : QCIStoreMultiple<0b00, GPRNoX0, "qc.swm">;
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def QC_SWMI : QCIStoreMultiple<0b01, uimm5nonzero, "qc.swmi">;
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def QC_SETWM : QCIStoreMultiple<0b10, GPRNoX0, "qc.setwm">;
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def QC_SETWMI : QCIStoreMultiple<0b11, uimm5nonzero, "qc.setwmi">;
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def QC_LWM : QCILoadMultiple<0b00, GPRNoX0, "qc.lwm">;
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def QC_LWMI : QCILoadMultiple<0b01, uimm5nonzero, "qc.lwmi">;
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} // Predicates = [HasVendorXqcilsm, IsRV32], DecoderNamespace = "Xqcilsm"
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//===----------------------------------------------------------------------===//
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// Aliases
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//===----------------------------------------------------------------------===//
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let Predicates = [HasVendorXqcilsm, IsRV32] in {
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let EmitPriority = 0 in {
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def : InstAlias<"qc.swm $rs3, $rs2, (${rs1})",
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(QC_SWM GPR:$rs3, GPR:$rs1, GPRNoX0:$rs2, 0)>;
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def : InstAlias<"qc.swmi $rs3, $length, (${rs1})",
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(QC_SWMI GPR:$rs3, GPR:$rs1, uimm5nonzero:$length, 0)>;
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def : InstAlias<"qc.setwm $rs3, $rs2, (${rs1})",
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(QC_SETWM GPR:$rs3, GPR:$rs1, GPRNoX0:$rs2, 0)>;
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def : InstAlias<"qc.setwmi $rs3, $length, (${rs1})",
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(QC_SETWMI GPR:$rs3, GPR:$rs1, uimm5nonzero:$length, 0)>;
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def : InstAlias<"qc.lwm $rd, $rs2, (${rs1})",
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(QC_LWM GPRNoX0:$rd, GPR:$rs1, GPRNoX0:$rs2, 0)>;
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def : InstAlias<"qc.lwmi $rd, $length, (${rs1})",
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(QC_LWMI GPRNoX0:$rd, GPR:$rs1, uimm5nonzero:$length, 0)>;
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} // EmitPriority = 0
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} // Predicates = [HasVendorXqcilsm, IsRV32]

‎llvm/lib/TargetParser/RISCVISAInfo.cpp‎

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@@ -742,7 +742,7 @@ Error RISCVISAInfo::checkDependency() {
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bool HasZvl = MinVLen != 0;
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bool HasZcmt = Exts.count("zcmt") != 0;
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static constexpr StringLiteral XqciExts[] = {
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{"xqcia"}, {"xqcics"}, {"xqcicsr"}, {"xqcisls"}};
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{"xqcia"}, {"xqcics"}, {"xqcicsr"}, {"xqcilsm"}, {"xqcisls"}};
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if (HasI && HasE)
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return getIncompatibleError("i", "e");

‎llvm/test/CodeGen/RISCV/attributes.ll‎

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@@ -84,6 +84,7 @@
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcia %s -o - | FileCheck --check-prefix=RV32XQCIA %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics %s -o - | FileCheck --check-prefix=RV32XQCICS %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicsr %s -o - | FileCheck --check-prefix=RV32XQCICSR %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilsm %s -o - | FileCheck --check-prefix=RV32XQCILSM %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcisls %s -o - | FileCheck --check-prefix=RV32XQCISLS %s
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; RUN: llc -mtriple=riscv32 -mattr=+zaamo %s -o - | FileCheck --check-prefix=RV32ZAAMO %s
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; RUN: llc -mtriple=riscv32 -mattr=+zalrsc %s -o - | FileCheck --check-prefix=RV32ZALRSC %s
@@ -392,6 +393,7 @@
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; RV32XQCIA: .attribute 5, "rv32i2p1_xqcia0p2"
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; RV32XQCICS: .attribute 5, "rv32i2p1_xqcics0p2"
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; RV32XQCICSR: .attribute 5, "rv32i2p1_xqcicsr0p2"
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; RV32XQCILSM: .attribute 5, "rv32i2p1_xqcilsm0p2"
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; RV32XQCISLS: .attribute 5, "rv32i2p1_xqcisls0p2"
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; RV32ZAAMO: .attribute 5, "rv32i2p1_zaamo1p0"
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; RV32ZALRSC: .attribute 5, "rv32i2p1_zalrsc1p0"

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