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kosarevkosarev
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[AMDGPU][NFC] Remove _DEFERRED operands. (#139123)
All immediates are deferred now.
1 parent cdde6a6 commit 66d3980

15 files changed

+45
-181
lines changed

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp‎

Lines changed: 5 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -1956,7 +1956,6 @@ static const fltSemantics *getOpFltSemantics(uint8_t OperandType) {
19561956
case AMDGPU::OPERAND_REG_INLINE_C_INT16:
19571957
case AMDGPU::OPERAND_REG_IMM_INT32:
19581958
case AMDGPU::OPERAND_REG_IMM_FP32:
1959-
case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:
19601959
case AMDGPU::OPERAND_REG_INLINE_C_INT32:
19611960
case AMDGPU::OPERAND_REG_INLINE_C_FP32:
19621961
case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
@@ -1975,14 +1974,12 @@ static const fltSemantics *getOpFltSemantics(uint8_t OperandType) {
19751974
case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
19761975
return &APFloat::IEEEdouble();
19771976
case AMDGPU::OPERAND_REG_IMM_FP16:
1978-
case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:
19791977
case AMDGPU::OPERAND_REG_INLINE_C_FP16:
19801978
case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
19811979
case AMDGPU::OPERAND_REG_IMM_V2FP16:
19821980
case AMDGPU::OPERAND_KIMM16:
19831981
return &APFloat::IEEEhalf();
19841982
case AMDGPU::OPERAND_REG_IMM_BF16:
1985-
case AMDGPU::OPERAND_REG_IMM_BF16_DEFERRED:
19861983
case AMDGPU::OPERAND_REG_INLINE_C_BF16:
19871984
case AMDGPU::OPERAND_REG_INLINE_C_V2BF16:
19881985
case AMDGPU::OPERAND_REG_IMM_V2BF16:
@@ -2304,7 +2301,6 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
23042301
llvm_unreachable("fp literal in 64-bit integer instruction.");
23052302

23062303
case AMDGPU::OPERAND_REG_IMM_BF16:
2307-
case AMDGPU::OPERAND_REG_IMM_BF16_DEFERRED:
23082304
case AMDGPU::OPERAND_REG_INLINE_C_BF16:
23092305
case AMDGPU::OPERAND_REG_INLINE_C_V2BF16:
23102306
case AMDGPU::OPERAND_REG_IMM_V2BF16:
@@ -2321,14 +2317,12 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
23212317

23222318
case AMDGPU::OPERAND_REG_IMM_INT32:
23232319
case AMDGPU::OPERAND_REG_IMM_FP32:
2324-
case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:
23252320
case AMDGPU::OPERAND_REG_INLINE_C_INT32:
23262321
case AMDGPU::OPERAND_REG_INLINE_C_FP32:
23272322
case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
23282323
case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
23292324
case AMDGPU::OPERAND_REG_IMM_INT16:
23302325
case AMDGPU::OPERAND_REG_IMM_FP16:
2331-
case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:
23322326
case AMDGPU::OPERAND_REG_INLINE_C_INT16:
23332327
case AMDGPU::OPERAND_REG_INLINE_C_FP16:
23342328
case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
@@ -2369,7 +2363,6 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
23692363
switch (OpTy) {
23702364
case AMDGPU::OPERAND_REG_IMM_INT32:
23712365
case AMDGPU::OPERAND_REG_IMM_FP32:
2372-
case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:
23732366
case AMDGPU::OPERAND_REG_INLINE_C_INT32:
23742367
case AMDGPU::OPERAND_REG_INLINE_C_FP32:
23752368
case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
@@ -2425,7 +2418,6 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
24252418

24262419
case AMDGPU::OPERAND_REG_INLINE_C_FP16:
24272420
case AMDGPU::OPERAND_REG_IMM_FP16:
2428-
case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:
24292421
if (isSafeTruncation(Val, 16) &&
24302422
AMDGPU::isInlinableLiteralFP16(static_cast<int16_t>(Val),
24312423
AsmParser->hasInv2PiInlineImm())) {
@@ -2439,7 +2431,6 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
24392431
return;
24402432

24412433
case AMDGPU::OPERAND_REG_IMM_BF16:
2442-
case AMDGPU::OPERAND_REG_IMM_BF16_DEFERRED:
24432434
case AMDGPU::OPERAND_REG_INLINE_C_BF16:
24442435
if (isSafeTruncation(Val, 16) &&
24452436
AMDGPU::isInlinableLiteralBF16(static_cast<int16_t>(Val),
@@ -3615,13 +3606,11 @@ bool AMDGPUAsmParser::isInlineConstant(const MCInst &Inst,
36153606
return AMDGPU::isInlinableLiteralV2BF16(Val);
36163607

36173608
if (OperandType == AMDGPU::OPERAND_REG_IMM_FP16 ||
3618-
OperandType == AMDGPU::OPERAND_REG_INLINE_C_FP16 ||
3619-
OperandType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED)
3609+
OperandType == AMDGPU::OPERAND_REG_INLINE_C_FP16)
36203610
return AMDGPU::isInlinableLiteralFP16(Val, hasInv2PiInlineImm());
36213611

36223612
if (OperandType == AMDGPU::OPERAND_REG_IMM_BF16 ||
3623-
OperandType == AMDGPU::OPERAND_REG_INLINE_C_BF16 ||
3624-
OperandType == AMDGPU::OPERAND_REG_IMM_BF16_DEFERRED)
3613+
OperandType == AMDGPU::OPERAND_REG_INLINE_C_BF16)
36253614
return AMDGPU::isInlinableLiteralBF16(Val, hasInv2PiInlineImm());
36263615

36273616
llvm_unreachable("invalid operand type");
@@ -3671,15 +3660,14 @@ static OperandIndices getSrcOperandIndices(unsigned Opcode,
36713660
AddMandatoryLiterals ? getNamedOperandIdx(Opcode, OpName::imm) : -1;
36723661

36733662
if (isVOPD(Opcode)) {
3674-
int16_t ImmDeferredIdx =
3675-
AddMandatoryLiterals ? getNamedOperandIdx(Opcode, OpName::immDeferred)
3676-
: -1;
3663+
int16_t ImmXIdx =
3664+
AddMandatoryLiterals ? getNamedOperandIdx(Opcode, OpName::immX) : -1;
36773665

36783666
return {getNamedOperandIdx(Opcode, OpName::src0X),
36793667
getNamedOperandIdx(Opcode, OpName::vsrc1X),
36803668
getNamedOperandIdx(Opcode, OpName::src0Y),
36813669
getNamedOperandIdx(Opcode, OpName::vsrc1Y),
3682-
ImmDeferredIdx,
3670+
ImmXIdx,
36833671
ImmIdx};
36843672
}
36853673

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp‎

Lines changed: 7 additions & 55 deletions
Original file line numberDiff line numberDiff line change
@@ -238,13 +238,6 @@ static DecodeStatus decodeSrcRegOrImmA9(MCInst &Inst, unsigned Imm,
238238
return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm | 512, Decoder);
239239
}
240240

241-
template <unsigned OpWidth>
242-
static DecodeStatus decodeSrcRegOrImmDeferred9(MCInst &Inst, unsigned Imm,
243-
uint64_t /* Addr */,
244-
const MCDisassembler *Decoder) {
245-
return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, Decoder);
246-
}
247-
248241
// Default decoders generated by tablegen: 'Decode<RegClass>RegisterClass'
249242
// when RegisterClass is used as an operand. Most often used for destination
250243
// operands.
@@ -324,22 +317,6 @@ static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm,
324317
return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(OpWidth, Imm & 0xFF));
325318
}
326319

327-
template <unsigned OpWidth>
328-
static DecodeStatus
329-
decodeOperand_VSrcT16_Lo128_Deferred(MCInst &Inst, unsigned Imm,
330-
uint64_t /*Addr*/,
331-
const MCDisassembler *Decoder) {
332-
const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
333-
assert(isUInt<9>(Imm) && "9-bit encoding expected");
334-
335-
if (Imm & AMDGPU::EncValues::IS_VGPR) {
336-
bool IsHi = Imm & (1 << 7);
337-
unsigned RegIdx = Imm & 0x7f;
338-
return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
339-
}
340-
return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(OpWidth, Imm & 0xFF));
341-
}
342-
343320
template <unsigned OpWidth>
344321
static DecodeStatus decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm,
345322
uint64_t /*Addr*/,
@@ -559,31 +536,21 @@ void AMDGPUDisassembler::decodeImmOperands(MCInst &MI,
559536
}
560537

561538
if (Imm == AMDGPU::EncValues::LITERAL_CONST) {
562-
switch (OpDesc.OperandType) {
563-
case AMDGPU::OPERAND_REG_IMM_BF16_DEFERRED:
564-
case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:
565-
case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:
566-
Op = MCOperand::createImm(AMDGPU::EncValues::LITERAL_CONST);
567-
continue;
568-
default:
569-
Op = decodeLiteralConstant(OpDesc.OperandType ==
570-
AMDGPU::OPERAND_REG_IMM_FP64);
571-
continue;
572-
}
539+
Op = decodeLiteralConstant(OpDesc.OperandType ==
540+
AMDGPU::OPERAND_REG_IMM_FP64);
541+
continue;
573542
}
574543

575544
if (AMDGPU::EncValues::INLINE_FLOATING_C_MIN <= Imm &&
576545
Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX) {
577546
switch (OpDesc.OperandType) {
578547
case AMDGPU::OPERAND_REG_IMM_BF16:
579-
case AMDGPU::OPERAND_REG_IMM_BF16_DEFERRED:
580548
case AMDGPU::OPERAND_REG_IMM_V2BF16:
581549
case AMDGPU::OPERAND_REG_INLINE_C_BF16:
582550
case AMDGPU::OPERAND_REG_INLINE_C_V2BF16:
583551
Imm = getInlineImmValBF16(Imm);
584552
break;
585553
case AMDGPU::OPERAND_REG_IMM_FP16:
586-
case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:
587554
case AMDGPU::OPERAND_REG_IMM_INT16:
588555
case AMDGPU::OPERAND_REG_IMM_V2FP16:
589556
case AMDGPU::OPERAND_REG_INLINE_C_FP16:
@@ -894,11 +861,9 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
894861
}
895862
}
896863

897-
int ImmLitIdx =
898-
AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm);
899864
bool IsSOPK = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::SOPK;
900-
if (ImmLitIdx != -1 && !IsSOPK)
901-
convertFMAanyK(MI, ImmLitIdx);
865+
if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::imm) && !IsSOPK)
866+
convertFMAanyK(MI);
902867

903868
// Some VOPC instructions, e.g., v_cmpx_f_f64, use VOP3 encoding and
904869
// have EXEC as implicit destination. Issue a warning if encoding for
@@ -1380,22 +1345,9 @@ void AMDGPUDisassembler::convertVOPC64DPPInst(MCInst &MI) const {
13801345
}
13811346
}
13821347

1383-
void AMDGPUDisassembler::convertFMAanyK(MCInst &MI, int ImmLitIdx) const {
1348+
void AMDGPUDisassembler::convertFMAanyK(MCInst &MI) const {
13841349
assert(HasLiteral && "Should have decoded a literal");
1385-
const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
1386-
unsigned DescNumOps = Desc.getNumOperands();
1387-
insertNamedMCOperand(MI, MCOperand::createImm(Literal),
1388-
AMDGPU::OpName::immDeferred);
1389-
assert(DescNumOps == MI.getNumOperands());
1390-
for (unsigned I = 0; I < DescNumOps; ++I) {
1391-
auto &Op = MI.getOperand(I);
1392-
auto OpType = Desc.operands()[I].OperandType;
1393-
bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED ||
1394-
OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED);
1395-
if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST &&
1396-
IsDeferredOp)
1397-
Op.setImm(Literal);
1398-
}
1350+
insertNamedMCOperand(MI, MCOperand::createImm(Literal), AMDGPU::OpName::immX);
13991351
}
14001352

14011353
const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const {

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -174,7 +174,7 @@ class AMDGPUDisassembler : public MCDisassembler {
174174

175175
void convertEXPInst(MCInst &MI) const;
176176
void convertVINTERPInst(MCInst &MI) const;
177-
void convertFMAanyK(MCInst &MI, int ImmLitIdx) const;
177+
void convertFMAanyK(MCInst &MI) const;
178178
void convertSDWAInst(MCInst &MI) const;
179179
void convertMAIInst(MCInst &MI) const;
180180
void convertDPP8Inst(MCInst &MI) const;

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -715,7 +715,6 @@ void AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo,
715715
switch (OpTy) {
716716
case AMDGPU::OPERAND_REG_IMM_INT32:
717717
case AMDGPU::OPERAND_REG_IMM_FP32:
718-
case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:
719718
case AMDGPU::OPERAND_REG_INLINE_C_INT32:
720719
case AMDGPU::OPERAND_REG_INLINE_C_FP32:
721720
case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
@@ -741,12 +740,10 @@ void AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo,
741740
break;
742741
case AMDGPU::OPERAND_REG_INLINE_C_FP16:
743742
case AMDGPU::OPERAND_REG_IMM_FP16:
744-
case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:
745743
printImmediateF16(Op.getImm(), STI, O);
746744
break;
747745
case AMDGPU::OPERAND_REG_INLINE_C_BF16:
748746
case AMDGPU::OPERAND_REG_IMM_BF16:
749-
case AMDGPU::OPERAND_REG_IMM_BF16_DEFERRED:
750747
printImmediateBF16(Op.getImm(), STI, O);
751748
break;
752749
case AMDGPU::OPERAND_REG_IMM_V2INT16:

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -273,7 +273,6 @@ AMDGPUMCCodeEmitter::getLitEncoding(const MCOperand &MO,
273273
switch (OpInfo.OperandType) {
274274
case AMDGPU::OPERAND_REG_IMM_INT32:
275275
case AMDGPU::OPERAND_REG_IMM_FP32:
276-
case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:
277276
case AMDGPU::OPERAND_REG_INLINE_C_INT32:
278277
case AMDGPU::OPERAND_REG_INLINE_C_FP32:
279278
case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
@@ -295,14 +294,12 @@ AMDGPUMCCodeEmitter::getLitEncoding(const MCOperand &MO,
295294
return getLit16IntEncoding(static_cast<uint32_t>(Imm), STI);
296295

297296
case AMDGPU::OPERAND_REG_IMM_FP16:
298-
case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:
299297
case AMDGPU::OPERAND_REG_INLINE_C_FP16:
300298
// FIXME Is this correct? What do inline immediates do on SI for f16 src
301299
// which does not have f16 support?
302300
return getLit16Encoding(static_cast<uint16_t>(Imm), STI);
303301

304302
case AMDGPU::OPERAND_REG_IMM_BF16:
305-
case AMDGPU::OPERAND_REG_IMM_BF16_DEFERRED:
306303
case AMDGPU::OPERAND_REG_INLINE_C_BF16:
307304
// We don't actually need to check Inv2Pi here because BF16 instructions can
308305
// only be emitted for targets that already support the feature.

‎llvm/lib/Target/AMDGPU/SIDefines.h‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -204,9 +204,6 @@ enum OperandType : unsigned {
204204
OPERAND_REG_IMM_FP64,
205205
OPERAND_REG_IMM_BF16,
206206
OPERAND_REG_IMM_FP16,
207-
OPERAND_REG_IMM_BF16_DEFERRED,
208-
OPERAND_REG_IMM_FP16_DEFERRED,
209-
OPERAND_REG_IMM_FP32_DEFERRED,
210207
OPERAND_REG_IMM_V2BF16,
211208
OPERAND_REG_IMM_V2FP16,
212209
OPERAND_REG_IMM_V2INT16,

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4376,7 +4376,6 @@ bool SIInstrInfo::isInlineConstant(int64_t Imm, uint8_t OperandType) const {
43764376
switch (OperandType) {
43774377
case AMDGPU::OPERAND_REG_IMM_INT32:
43784378
case AMDGPU::OPERAND_REG_IMM_FP32:
4379-
case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:
43804379
case AMDGPU::OPERAND_REG_INLINE_C_INT32:
43814380
case AMDGPU::OPERAND_REG_INLINE_C_FP32:
43824381
case AMDGPU::OPERAND_REG_IMM_V2FP32:
@@ -4416,7 +4415,6 @@ bool SIInstrInfo::isInlineConstant(int64_t Imm, uint8_t OperandType) const {
44164415
case AMDGPU::OPERAND_REG_INLINE_C_V2BF16:
44174416
return AMDGPU::isInlinableLiteralV2BF16(Imm);
44184417
case AMDGPU::OPERAND_REG_IMM_FP16:
4419-
case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:
44204418
case AMDGPU::OPERAND_REG_INLINE_C_FP16: {
44214419
if (isInt<16>(Imm) || isUInt<16>(Imm)) {
44224420
// A few special case instructions have 16-bit operands on subtargets
@@ -4431,7 +4429,6 @@ bool SIInstrInfo::isInlineConstant(int64_t Imm, uint8_t OperandType) const {
44314429
return false;
44324430
}
44334431
case AMDGPU::OPERAND_REG_IMM_BF16:
4434-
case AMDGPU::OPERAND_REG_IMM_BF16_DEFERRED:
44354432
case AMDGPU::OPERAND_REG_INLINE_C_BF16: {
44364433
if (isInt<16>(Imm) || isUInt<16>(Imm)) {
44374434
int16_t Trunc = static_cast<int16_t>(Imm);
@@ -4842,7 +4839,6 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
48424839
break;
48434840
case AMDGPU::OPERAND_REG_IMM_INT32:
48444841
case AMDGPU::OPERAND_REG_IMM_FP32:
4845-
case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:
48464842
case AMDGPU::OPERAND_REG_IMM_V2FP32:
48474843
break;
48484844
case AMDGPU::OPERAND_REG_INLINE_C_INT32:

‎llvm/lib/Target/AMDGPU/SIInstrInfo.td‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2701,13 +2701,11 @@ class VOPProfile <list<ValueType> _ArgVT, bit _EnableClamp = 0> {
27012701
HasSDWAOMod, Src0ModSDWA, Src1ModSDWA,
27022702
DstVT>.ret;
27032703
field dag InsVOPDX = (ins Src0RC32:$src0X, Src1RC32:$vsrc1X);
2704-
// It is a slight misnomer to use the deferred f32 operand type for non-float
2704+
// It is a slight misnomer to use the f32 operand type for non-float
27052705
// operands, but this operand type will only be used if the other dual
27062706
// component is FMAAK or FMAMK
2707-
field dag InsVOPDXDeferred = (ins !if(!eq(Src0VT.Size, 32), VSrc_f32_Deferred, VSrc_f16_Deferred):$src0X, VGPR_32:$vsrc1X);
2707+
field dag InsVOPDX_immX = (ins !if(!eq(Src0VT.Size, 32), VSrc_f32, VSrc_f16):$src0X, VGPR_32:$vsrc1X);
27082708
field dag InsVOPDY = (ins Src0RC32:$src0Y, Src1RC32:$vsrc1Y);
2709-
field dag InsVOPDYDeferred = (ins !if(!eq(Src1VT.Size, 32), VSrc_f32_Deferred, VSrc_f16_Deferred):$src0Y, VGPR_32:$vsrc1Y);
2710-
27112709

27122710
field string Asm32 = getAsm32<HasDst, NumSrcArgs, DstVT>.ret;
27132711
field string AsmDPP = !if(HasExtDPP,

‎llvm/lib/Target/AMDGPU/SIRegisterInfo.td‎

Lines changed: 1 addition & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -1100,7 +1100,7 @@ class RegOrImmOperand <RegisterClass RegClass, string OperandTypeName>
11001100
: RegisterOperand<RegClass> {
11011101
let OperandNamespace = "AMDGPU";
11021102
let OperandType = OperandTypeName;
1103-
let ParserMatchClass = RegImmMatcher<!subst("_Deferred", "", NAME)>;
1103+
let ParserMatchClass = RegImmMatcher<NAME>;
11041104
}
11051105

11061106
//===----------------------------------------------------------------------===//
@@ -1128,19 +1128,6 @@ def SSrc_b64 : SrcRegOrImm9 <SReg_64, "OPERAND_REG_IMM_INT64">;
11281128

11291129
def SSrcOrLds_b32 : SrcRegOrImm9 <SRegOrLds_32, "OPERAND_REG_IMM_INT32">;
11301130

1131-
//===----------------------------------------------------------------------===//
1132-
// SSrc_32_Deferred Operands with an SGPR or a 32-bit immediate for use with
1133-
// FMAMK/FMAAK
1134-
//===----------------------------------------------------------------------===//
1135-
1136-
class SrcRegOrImmDeferred9<RegisterClass regClass, string operandType>
1137-
: RegOrImmOperand<regClass, operandType> {
1138-
string DecoderMethodName = "decodeSrcRegOrImmDeferred9";
1139-
let DecoderMethod = DecoderMethodName # "<" # regClass.Size # ">";
1140-
}
1141-
1142-
def SSrc_f32_Deferred : SrcRegOrImmDeferred9<SReg_32, "OPERAND_REG_IMM_FP32_DEFERRED">;
1143-
11441131
//===----------------------------------------------------------------------===//
11451132
// SCSrc_* Operands with an SGPR or a inline constant
11461133
//===----------------------------------------------------------------------===//
@@ -1187,27 +1174,6 @@ def VSrc_f64 : SrcRegOrImm9 <VS_64, "OPERAND_REG_IMM_FP64"> {
11871174
def VSrc_v2b32 : SrcRegOrImm9 <VS_64, "OPERAND_REG_IMM_V2INT32">;
11881175
def VSrc_v2f32 : SrcRegOrImm9 <VS_64, "OPERAND_REG_IMM_V2FP32">;
11891176

1190-
//===----------------------------------------------------------------------===//
1191-
// VSrc_*_Deferred Operands with an SGPR, VGPR or a 32-bit immediate for use
1192-
// with FMAMK/FMAAK
1193-
//===----------------------------------------------------------------------===//
1194-
1195-
def VSrc_bf16_Deferred : SrcRegOrImmDeferred9<VS_32, "OPERAND_REG_IMM_BF16_DEFERRED">;
1196-
def VSrc_f16_Deferred : SrcRegOrImmDeferred9<VS_32, "OPERAND_REG_IMM_FP16_DEFERRED">;
1197-
def VSrc_f32_Deferred : SrcRegOrImmDeferred9<VS_32, "OPERAND_REG_IMM_FP32_DEFERRED">;
1198-
1199-
// True 16 Operands
1200-
def VSrcT_f16_Lo128_Deferred : SrcRegOrImmDeferred9<VS_16_Lo128,
1201-
"OPERAND_REG_IMM_FP16_DEFERRED"> {
1202-
let DecoderMethodName = "decodeOperand_VSrcT16_Lo128_Deferred";
1203-
let EncoderMethod = "getMachineOpValueT16Lo128";
1204-
}
1205-
1206-
def VSrcFake16_bf16_Lo128_Deferred
1207-
: SrcRegOrImmDeferred9<VS_32_Lo128, "OPERAND_REG_IMM_BF16_DEFERRED">;
1208-
def VSrcFake16_f16_Lo128_Deferred
1209-
: SrcRegOrImmDeferred9<VS_32_Lo128, "OPERAND_REG_IMM_FP16_DEFERRED">;
1210-
12111177
//===----------------------------------------------------------------------===//
12121178
// VRegSrc_* Operands with a VGPR
12131179
//===----------------------------------------------------------------------===//

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