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[WebAssembly] Add patterns for extadd pairwise (#167960)
Add a few patterns for extadd pairwise.
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‎llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td‎

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@@ -1541,6 +1541,32 @@ def : Pat<(v4i32 (int_wasm_extadd_pairwise_signed (v8i16 V128:$in))),
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def : Pat<(v8i16 (int_wasm_extadd_pairwise_signed (v16i8 V128:$in))),
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(extadd_pairwise_s_I16x8 V128:$in)>;
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multiclass ExtAddPairwiseShuffle<ValueType from_ty, ValueType to_ty, string suffix,
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int a0, int a1, int a2, int a3, int a4, int a5, int a6, int a7,
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int b0, int b1, int b2, int b3, int b4, int b5, int b6, int b7> {
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foreach sign = ["s", "u"] in {
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def : Pat<(to_ty (add
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(!cast<SDNode>("extend_low_"#sign) (from_ty (wasm_shuffle (from_ty V128:$vec), (from_ty srcvalue),
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(i32 a0), (i32 a1), (i32 a2), (i32 a3),
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(i32 a4), (i32 a5), (i32 a6), (i32 a7),
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(i32 srcvalue), (i32 srcvalue), (i32 srcvalue), (i32 srcvalue),
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(i32 srcvalue), (i32 srcvalue), (i32 srcvalue), (i32 srcvalue)))),
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(!cast<SDNode>("extend_low_"#sign) (from_ty (wasm_shuffle (from_ty V128:$vec), (from_ty srcvalue),
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(i32 b0), (i32 b1), (i32 b2), (i32 b3),
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(i32 b4), (i32 b5), (i32 b6), (i32 b7),
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(i32 srcvalue), (i32 srcvalue), (i32 srcvalue), (i32 srcvalue),
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(i32 srcvalue), (i32 srcvalue), (i32 srcvalue), (i32 srcvalue)))))),
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(!cast<Instruction>("extadd_pairwise_"#sign#"_"#suffix) V128:$vec)>;
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}
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}
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defm : ExtAddPairwiseShuffle<v8i16, v4i32, "I32x4",
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0, 1, 4, 5, 8, 9, 12, 13,
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2, 3, 6, 7, 10, 11, 14, 15>;
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defm : ExtAddPairwiseShuffle<v16i8, v8i16, "I16x8",
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0, 2, 4, 6, 8, 10, 12, 14,
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1, 3, 5, 7, 9, 11, 13, 15>;
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// f64x2 <-> f32x4 conversions
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def demote_t : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>;
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def demote_zero : SDNode<"WebAssemblyISD::DEMOTE_ZERO", demote_t>;

‎llvm/test/CodeGen/WebAssembly/simd-extadd.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc < %s -O2 -mtriple=wasm32 -mattr=+simd128 | FileCheck %s
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target triple = "wasm32-unknown-unknown"
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; Test that adding two extended shuffles from the same vector that ends w/ an add converts to extadd_pairwise
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define <8 x i16> @test_extadd_pairwise_i8x16_s(<16 x i8> %v) {
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; CHECK-LABEL: test_extadd_pairwise_i8x16_s:
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; CHECK: .functype test_extadd_pairwise_i8x16_s (v128) -> (v128)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: i16x8.extadd_pairwise_i8x16_s
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; CHECK-NEXT: # fallthrough-return
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%even = shufflevector <16 x i8> %v, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%odd = shufflevector <16 x i8> %v, <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%even_ext = sext <8 x i8> %even to <8 x i16>
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%odd_ext = sext <8 x i8> %odd to <8 x i16>
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%result = add <8 x i16> %even_ext, %odd_ext
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ret <8 x i16> %result
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}
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define <8 x i16> @test_extadd_pairwise_i8x16_u(<16 x i8> %v) {
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; CHECK-LABEL: test_extadd_pairwise_i8x16_u:
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; CHECK: .functype test_extadd_pairwise_i8x16_u (v128) -> (v128)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: i16x8.extadd_pairwise_i8x16_u
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; CHECK-NEXT: # fallthrough-return
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%even = shufflevector <16 x i8> %v, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%odd = shufflevector <16 x i8> %v, <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%even_ext = zext <8 x i8> %even to <8 x i16>
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%odd_ext = zext <8 x i8> %odd to <8 x i16>
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%result = add <8 x i16> %even_ext, %odd_ext
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ret <8 x i16> %result
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}
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define <4 x i32> @test_extadd_pairwise_i16x8_s(<8 x i16> %v) {
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; CHECK-LABEL: test_extadd_pairwise_i16x8_s:
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; CHECK: .functype test_extadd_pairwise_i16x8_s (v128) -> (v128)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: i32x4.extadd_pairwise_i16x8_s
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; CHECK-NEXT: # fallthrough-return
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%even = shufflevector <8 x i16> %v, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%odd = shufflevector <8 x i16> %v, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%even_ext = sext <4 x i16> %even to <4 x i32>
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%odd_ext = sext <4 x i16> %odd to <4 x i32>
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%result = add <4 x i32> %even_ext, %odd_ext
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ret <4 x i32> %result
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}
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define <4 x i32> @test_extadd_pairwise_i16x8_u(<8 x i16> %v) {
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; CHECK-LABEL: test_extadd_pairwise_i16x8_u:
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; CHECK: .functype test_extadd_pairwise_i16x8_u (v128) -> (v128)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: i32x4.extadd_pairwise_i16x8_u
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; CHECK-NEXT: # fallthrough-return
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%even = shufflevector <8 x i16> %v, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%odd = shufflevector <8 x i16> %v, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%even_ext = zext <4 x i16> %even to <4 x i32>
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%odd_ext = zext <4 x i16> %odd to <4 x i32>
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%result = add <4 x i32> %even_ext, %odd_ext
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ret <4 x i32> %result
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}
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; Negative test: shuffling mask doesn't fit pattern
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define <4 x i32> @negative_test_extadd_pairwise_i16x8_u(<8 x i16> %v) {
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; CHECK-LABEL: negative_test_extadd_pairwise_i16x8_u:
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; CHECK: .functype negative_test_extadd_pairwise_i16x8_u (v128) -> (v128)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: i8x16.shuffle 0, 1, 6, 7, 8, 9, 12, 13, 0, 1, 0, 1, 0, 1, 0, 1
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; CHECK-NEXT: i32x4.extend_low_i16x8_u
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: i8x16.shuffle 2, 3, 6, 7, 10, 11, 14, 15, 0, 1, 0, 1, 0, 1, 0, 1
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; CHECK-NEXT: i32x4.extend_low_i16x8_u
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; CHECK-NEXT: i32x4.add
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; CHECK-NEXT: # fallthrough-return
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%even = shufflevector <8 x i16> %v, <8 x i16> poison, <4 x i32> <i32 0, i32 3, i32 4, i32 6>
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%odd = shufflevector <8 x i16> %v, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%even_ext = zext <4 x i16> %even to <4 x i32>
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%odd_ext = zext <4 x i16> %odd to <4 x i32>
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%result = add <4 x i32> %even_ext, %odd_ext
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ret <4 x i32> %result
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}

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