[RISCV][LLVM] Atomic load min/max pseudo expansion

When the 'Zbb' extension is present it provides min(u)/max(u) instructions.
Use these if available in the 'Zalrsc' atomic load min/max pseudo expansions,
since they result in smaller and faster code.  When 'Zbb' is not present
continue to use the longer branch based expansion path.

Author: slachowsky

llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp

@@ -324,6 +324,9 @@ static void doAtomicBinOpExpansion(const RISCVInstrInfo *TII, MachineInstr &MI,
   Register ScratchReg = MI.getOperand(1).getReg();
   Register AddrReg = MI.getOperand(2).getReg();
   Register IncrReg = MI.getOperand(3).getReg();
+  bool IsUnsigned = BinOp == AtomicRMWInst::UMin ||
+                    BinOp == AtomicRMWInst::UMax;
+  bool Zext = IsUnsigned && STI->is64Bit() && Width == 32;
   AtomicOrdering Ordering =
       static_cast<AtomicOrdering>(MI.getOperand(4).getImm());
 
@@ -375,6 +378,34 @@ static void doAtomicBinOpExpansion(const RISCVInstrInfo *TII, MachineInstr &MI,
         .addReg(ScratchReg)
         .addImm(-1);
     break;
+  case AtomicRMWInst::Min:
+    BuildMI(LoopMBB, DL, TII->get(RISCV::MIN), ScratchReg)
+        .addReg(DestReg)
+        .addReg(IncrReg);
+    break;
+  case AtomicRMWInst::Max:
+    BuildMI(LoopMBB, DL, TII->get(RISCV::MAX), ScratchReg)
+        .addReg(DestReg)
+        .addReg(IncrReg);
+    break;
+  case AtomicRMWInst::UMin:
+    if (Zext)
+      BuildMI(LoopMBB, DL, TII->get(RISCV::ADD_UW), ScratchReg)
+          .addReg(DestReg)
+          .addReg(RISCV::X0);
+    BuildMI(LoopMBB, DL, TII->get(RISCV::MINU), ScratchReg)
+        .addReg(Zext ? ScratchReg : DestReg)
+        .addReg(IncrReg);
+    break;
+  case AtomicRMWInst::UMax:
+    if (Zext)
+      BuildMI(LoopMBB, DL, TII->get(RISCV::ADD_UW), ScratchReg)
+          .addReg(DestReg)
+          .addReg(RISCV::X0);
+    BuildMI(LoopMBB, DL, TII->get(RISCV::MAXU), ScratchReg)
+        .addReg(Zext ? ScratchReg : DestReg)
+        .addReg(IncrReg);
+    break;
   }
   BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width, STI)), ScratchReg)
       .addReg(ScratchReg)
@@ -705,6 +736,10 @@ bool RISCVExpandAtomicPseudo::expandAtomicMinMaxOp(
     AtomicRMWInst::BinOp BinOp, bool IsMasked, int Width,
     MachineBasicBlock::iterator &NextMBBI) {
 
+  // Prefer expansion using MIN/MAX/MINU/MAXU instructions if available
+  if (STI->hasStdExtZbb() && !IsMasked)
+    return expandAtomicBinOp(MBB, MBBI, BinOp, IsMasked, Width, NextMBBI);
+
   MachineInstr &MI = *MBBI;
   DebugLoc DL = MI.getDebugLoc();
   MachineFunction *MF = MBB.getParent();