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HendrikHuebnerHendrikHuebner
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Add test
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‎clang/test/CIR/CodeGen/atomic-thread-fence.c‎

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// RUN: %clang_cc1 -triple aarch64-none-linux-android21 -fclangir -emit-cir %s -o %t.cir
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// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s
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// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -emit-llvm %s -o %t.ll
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// RUN: FileCheck --check-prefix=LLVM --input-file=%t.ll %s
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// RUN: %clang_cc1 -triple aarch64-none-linux-android21 -emit-llvm %s -o %t.ll
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// RUN: FileCheck --check-prefix=OGCG --input-file=%t.ll %s
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struct Data {
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int value;
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void *ptr;
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};
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typedef struct Data *DataPtr;
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void applyThreadFence() {
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__atomic_thread_fence(__ATOMIC_SEQ_CST);
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// CIR-LABEL: @applyThreadFence
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// CIR: cir.atomic.fence syncscope(system) seq_cst
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// CIR: cir.return
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// LLVM-LABEL: @applyThreadFence
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// LLVM: fence seq_cst
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// LLVM: ret void
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// OGCG-LABEL: @applyThreadFence
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// OGCG: fence seq_cst
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// OGCG: ret void
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}
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void applySignalFence() {
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__atomic_signal_fence(__ATOMIC_SEQ_CST);
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// CIR-LABEL: @applySignalFence
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// CIR: cir.atomic.fence syncscope(single_thread) seq_cst
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// CIR: cir.return
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// LLVM-LABEL: @applySignalFence
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// LLVM: fence syncscope("singlethread") seq_cst
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// LLVM: ret void
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// OGCG-LABEL: @applySignalFence
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// OGCG: fence syncscope("singlethread") seq_cst
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// OGCG: ret void
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}
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void modifyWithThreadFence(DataPtr d) {
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__atomic_thread_fence(__ATOMIC_SEQ_CST);
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d->value = 42;
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// CIR-LABEL: @modifyWithThreadFence
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// CIR: %[[DATA:.*]] = cir.alloca !cir.ptr<!rec_Data>, !cir.ptr<!cir.ptr<!rec_Data>>, ["d", init] {alignment = 8 : i64}
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// CIR: cir.atomic.fence syncscope(system) seq_cst
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// CIR: %[[VAL_42:.*]] = cir.const #cir.int<42> : !s32i
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// CIR: %[[LOAD_DATA:.*]] = cir.load{{.*}} %[[DATA]] : !cir.ptr<!cir.ptr<!rec_Data>>, !cir.ptr<!rec_Data>
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// CIR: %[[DATA_VALUE:.*]] = cir.get_member %[[LOAD_DATA]][0] {name = "value"} : !cir.ptr<!rec_Data> -> !cir.ptr<!s32i>
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// CIR: cir.store{{.*}} %[[VAL_42]], %[[DATA_VALUE]] : !s32i, !cir.ptr<!s32i>
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// CIR: cir.return
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// LLVM-LABEL: @modifyWithThreadFence
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// LLVM: %[[DATA:.*]] = alloca ptr, i64 1, align 8
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// LLVM: fence seq_cst
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// LLVM: %[[DATA_PTR:.*]] = load ptr, ptr %[[DATA]], align 8
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// LLVM: %[[DATA_VALUE:.*]] = getelementptr %struct.Data, ptr %[[DATA_PTR]], i32 0, i32 0
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// LLVM: store i32 42, ptr %[[DATA_VALUE]], align 8
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// LLVM: ret void
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// OGCG-LABEL: @modifyWithThreadFence
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// OGCG: %[[DATA:.*]] = alloca ptr, align 8
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// OGCG: fence seq_cst
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// OGCG: %[[DATA_PTR:.*]] = load ptr, ptr %[[DATA]], align 8
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// OGCG: %[[DATA_VALUE:.*]] = getelementptr inbounds nuw %struct.Data, ptr %[[DATA_PTR]], i32 0, i32 0
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// OGCG: store i32 42, ptr %[[DATA_VALUE]], align 8
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// OGCG: ret void
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}
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void modifyWithSignalFence(DataPtr d) {
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__atomic_signal_fence(__ATOMIC_SEQ_CST);
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d->value = 24;
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// CIR-LABEL: @modifyWithSignalFence
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// CIR: %[[DATA:.*]] = cir.alloca !cir.ptr<!rec_Data>, !cir.ptr<!cir.ptr<!rec_Data>>, ["d", init] {alignment = 8 : i64}
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// CIR: cir.atomic.fence syncscope(single_thread) seq_cst
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// CIR: %[[VAL_42:.*]] = cir.const #cir.int<24> : !s32i
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// CIR: %[[LOAD_DATA:.*]] = cir.load{{.*}} %[[DATA]] : !cir.ptr<!cir.ptr<!rec_Data>>, !cir.ptr<!rec_Data>
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// CIR: %[[DATA_VALUE:.*]] = cir.get_member %[[LOAD_DATA]][0] {name = "value"} : !cir.ptr<!rec_Data> -> !cir.ptr<!s32i>
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// CIR: cir.store{{.*}} %[[VAL_42]], %[[DATA_VALUE]] : !s32i, !cir.ptr<!s32i>
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// CIR: cir.return
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// LLVM-LABEL: @modifyWithSignalFence
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// LLVM: %[[DATA:.*]] = alloca ptr, i64 1, align 8
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// LLVM: fence syncscope("singlethread") seq_cst
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// LLVM: %[[DATA_PTR:.*]] = load ptr, ptr %[[DATA]], align 8
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// LLVM: %[[DATA_VALUE:.*]] = getelementptr %struct.Data, ptr %[[DATA_PTR]], i32 0, i32 0
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// LLVM: store i32 24, ptr %[[DATA_VALUE]], align 8
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// LLVM: ret void
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// OGCG-LABEL: @modifyWithSignalFence
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// OGCG: %[[DATA:.*]] = alloca ptr, align 8
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// OGCG: fence syncscope("singlethread") seq_cst
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// OGCG: %[[DATA_PTR:.*]] = load ptr, ptr %[[DATA]], align 8
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// OGCG: %[[DATA_VALUE:.*]] = getelementptr inbounds nuw %struct.Data, ptr %[[DATA_PTR]], i32 0, i32 0
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// OGCG: store i32 24, ptr %[[DATA_VALUE]], align 8
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// OGCG: ret void
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}
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void loadWithThreadFence(DataPtr d) {
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__atomic_thread_fence(__ATOMIC_SEQ_CST);
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__atomic_load_n(&d->ptr, __ATOMIC_SEQ_CST);
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// CIR-LABEL: @loadWithThreadFence
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// CIR: %[[DATA:.*]] = cir.alloca !cir.ptr<!rec_Data>, !cir.ptr<!cir.ptr<!rec_Data>>, ["d", init] {alignment = 8 : i64}
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// CIR: %[[ATOMIC_TEMP:.*]] = cir.alloca !cir.ptr<!void>, !cir.ptr<!cir.ptr<!void>>, ["atomic-temp"] {alignment = 8 : i64}
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// CIR: cir.atomic.fence syncscope(system) seq_cst
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// CIR: %[[LOAD_DATA:.*]] = cir.load{{.*}} %[[DATA]] : !cir.ptr<!cir.ptr<!rec_Data>>, !cir.ptr<!rec_Data>
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// CIR: %[[DATA_VALUE:.*]] = cir.get_member %[[LOAD_DATA]][1] {name = "ptr"} : !cir.ptr<!rec_Data> -> !cir.ptr<!cir.ptr<!void>>
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// CIR: %[[CASTED_DATA_VALUE:.*]] = cir.cast bitcast %[[DATA_VALUE]] : !cir.ptr<!cir.ptr<!void>> -> !cir.ptr<!u64i>
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// CIR: %[[CASTED_ATOMIC_TEMP:.*]] = cir.cast bitcast %[[ATOMIC_TEMP]] : !cir.ptr<!cir.ptr<!void>> -> !cir.ptr<!u64i>
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// CIR: %[[ATOMIC_LOAD:.*]] = cir.load{{.*}} atomic(seq_cst) %[[CASTED_DATA_VALUE]] : !cir.ptr<!u64i>, !u64i
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// CIR: cir.store{{.*}} %[[ATOMIC_LOAD]], %[[CASTED_ATOMIC_TEMP]] : !u64i, !cir.ptr<!u64i>
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// CIR: %[[DOUBLE_CASTED_ATOMIC_TEMP:.*]] = cir.cast bitcast %[[CASTED_ATOMIC_TEMP]] : !cir.ptr<!u64i> -> !cir.ptr<!cir.ptr<!void>>
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// CIR: %[[ATOMIC_LOAD_PTR:.*]] = cir.load{{.*}} %[[DOUBLE_CASTED_ATOMIC_TEMP]] : !cir.ptr<!cir.ptr<!void>>, !cir.ptr<!void>
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// CIR: cir.return
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// LLVM-LABEL: @loadWithThreadFence
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// LLVM: %[[DATA:.*]] = alloca ptr, i64 1, align 8
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// LLVM: %[[DATA_TEMP:.*]] = alloca ptr, i64 1, align 8
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// LLVM: fence seq_cst
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// LLVM: %[[DATA_PTR:.*]] = load ptr, ptr %[[DATA]], align 8
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// LLVM: %[[DATA_VALUE:.*]] = getelementptr %struct.Data, ptr %[[DATA_PTR]], i32 0, i32 1
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// LLVM: %[[ATOMIC_LOAD:.*]] = load atomic i64, ptr %[[DATA_VALUE]] seq_cst, align 8
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// LLVM: store i64 %[[ATOMIC_LOAD]], ptr %[[DATA_TEMP]], align 8
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// LLVM: %[[DATA_TEMP_LOAD:.*]] = load ptr, ptr %[[DATA_TEMP]], align 8
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// LLVM: ret void
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// OGCG-LABEL: @loadWithThreadFence
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// OGCG: %[[DATA:.*]] = alloca ptr, align 8
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// OGCG: %[[DATA_TEMP:.*]] = alloca ptr, align 8
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// OGCG: fence seq_cst
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// OGCG: %[[DATA_PTR:.*]] = load ptr, ptr %[[DATA]], align 8
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// OGCG: %[[DATA_VALUE:.*]] = getelementptr inbounds nuw %struct.Data, ptr %[[DATA_PTR]], i32 0, i32 1
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// OGCG: %[[ATOMIC_LOAD:.*]] = load atomic i64, ptr %[[DATA_VALUE]] seq_cst, align 8
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// OGCG: store i64 %[[ATOMIC_LOAD]], ptr %[[DATA_TEMP]], align 8
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// OGCG: %[[DATA_TEMP_LOAD:.*]] = load ptr, ptr %[[DATA_TEMP]], align 8
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// OGCG: ret void
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}
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void loadWithSignalFence(DataPtr d) {
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__atomic_signal_fence(__ATOMIC_SEQ_CST);
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__atomic_load_n(&d->ptr, __ATOMIC_SEQ_CST);
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// CIR-LABEL: @loadWithSignalFence
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// CIR: %[[DATA:.*]] = cir.alloca !cir.ptr<!rec_Data>, !cir.ptr<!cir.ptr<!rec_Data>>, ["d", init] {alignment = 8 : i64}
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// CIR: %[[ATOMIC_TEMP:.*]] = cir.alloca !cir.ptr<!void>, !cir.ptr<!cir.ptr<!void>>, ["atomic-temp"] {alignment = 8 : i64}
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// CIR: cir.atomic.fence syncscope(single_thread) seq_cst
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// CIR: %[[LOAD_DATA:.*]] = cir.load{{.*}} %[[DATA]] : !cir.ptr<!cir.ptr<!rec_Data>>, !cir.ptr<!rec_Data>
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// CIR: %[[DATA_PTR:.*]] = cir.get_member %[[LOAD_DATA]][1] {name = "ptr"} : !cir.ptr<!rec_Data> -> !cir.ptr<!cir.ptr<!void>>
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// CIR: %[[CASTED_DATA_PTR:.*]] = cir.cast bitcast %[[DATA_PTR]] : !cir.ptr<!cir.ptr<!void>> -> !cir.ptr<!u64i>
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// CIR: %[[CASTED_ATOMIC_TEMP:.*]] = cir.cast bitcast %[[ATOMIC_TEMP]] : !cir.ptr<!cir.ptr<!void>> -> !cir.ptr<!u64i>
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// CIR: %[[ATOMIC_LOAD:.*]] = cir.load{{.*}} atomic(seq_cst) %[[CASTED_DATA_PTR]] : !cir.ptr<!u64i>, !u64i
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// CIR: cir.store{{.*}} %[[ATOMIC_LOAD]], %[[CASTED_ATOMIC_TEMP]] : !u64i, !cir.ptr<!u64i>
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// CIR: %[[DOUBLE_CASTED_ATOMIC_TEMP:.*]] = cir.cast bitcast %[[CASTED_ATOMIC_TEMP]] : !cir.ptr<!u64i> -> !cir.ptr<!cir.ptr<!void>>
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// CIR: %[[LOAD_ATOMIC_TEMP:.*]] = cir.load{{.*}} %[[DOUBLE_CASTED_ATOMIC_TEMP]] : !cir.ptr<!cir.ptr<!void>>, !cir.ptr<!void>
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// CIR: cir.return
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// LLVM-LABEL: @loadWithSignalFence
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// LLVM: %[[DATA:.*]] = alloca ptr, i64 1, align 8
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// LLVM: %[[DATA_TEMP:.*]] = alloca ptr, i64 1, align 8
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// LLVM: fence syncscope("singlethread") seq_cst
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// LLVM: %[[DATA_PTR:.*]] = load ptr, ptr %[[DATA]], align 8
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// LLVM: %[[DATA_VALUE:.*]] = getelementptr %struct.Data, ptr %[[DATA_PTR]], i32 0, i32 1
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// LLVM: %[[ATOMIC_LOAD:.*]] = load atomic i64, ptr %[[DATA_VALUE]] seq_cst, align 8
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// LLVM: store i64 %[[ATOMIC_LOAD]], ptr %[[DATA_TEMP]], align 8
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// LLVM: %[[DATA_TEMP_LOAD]] = load ptr, ptr %[[DATA_TEMP]], align 8
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// LLVM: ret void
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// OGCG-LABEL: @loadWithSignalFence
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// OGCG: %[[DATA:.*]] = alloca ptr, align 8
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// OGCG: %[[DATA_TEMP:.*]] = alloca ptr, align 8
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// OGCG: fence syncscope("singlethread") seq_cst
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// OGCG: %[[DATA_PTR:.*]] = load ptr, ptr %[[DATA]], align 8
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// OGCG: %[[DATA_VALUE:.*]] = getelementptr inbounds nuw %struct.Data, ptr %[[DATA_PTR]], i32 0, i32 1
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// OGCG: %[[ATOMIC_LOAD:.*]] = load atomic i64, ptr %[[DATA_VALUE]] seq_cst, align 8
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// OGCG: store i64 %[[ATOMIC_LOAD]], ptr %[[DATA_TEMP]], align 8
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// OGCG: %[[DATA_TEMP_LOAD]] = load ptr, ptr %[[DATA_TEMP]], align 8
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// OGCG: ret void
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}

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