@@ -520,8 +520,8 @@ NVPTX::Ordering NVPTXDAGToDAGISel::getMemOrder(const MemSDNode *N) const {
520520  auto  Ordering = N->getMergedOrdering ();
521521  switch  (Ordering) {
522522  case  AtomicOrdering::NotAtomic:
523-   case  AtomicOrdering::Unordered:
524523    return  NVPTX::Ordering::NotAtomic;
524+   case  AtomicOrdering::Unordered:
525525  case  AtomicOrdering::Monotonic:
526526    return  NVPTX::Ordering::Relaxed;
527527  case  AtomicOrdering::Acquire:
@@ -533,12 +533,14 @@ NVPTX::Ordering NVPTXDAGToDAGISel::getMemOrder(const MemSDNode *N) const {
533533  case  AtomicOrdering::SequentiallyConsistent:
534534    return  NVPTX::Ordering::SequentiallyConsistent;
535535  }
536+   llvm_unreachable (" Invalid atomic ordering"  );
536537}
537538
538539NVPTX::Scope NVPTXDAGToDAGISel::getAtomicScope (const  MemSDNode *N) const  {
539540  //  No "scope" modifier for SM/PTX versions which do not support scoped atomics
541+   //  Functionally, these atomics are at device scope
540542  if  (!Subtarget->hasAtomScope ())
541-     return  NVPTX::Scope::Thread ;
543+     return  NVPTX::Scope::DefaultDevice ;
542544  return  Scopes[N->getSyncScopeID ()];
543545}
544546
@@ -778,7 +780,7 @@ NVPTX::Scope NVPTXDAGToDAGISel::getOperationScope(MemSDNode *N,
778780}
779781
780782static  bool  canLowerToLDG (const  MemSDNode &N, const  NVPTXSubtarget &Subtarget,
781-                           unsigned  CodeAddrSpace) {
783+                           NVPTX::AddressSpace  CodeAddrSpace) {
782784  //  We use ldg (i.e. ld.global.nc) for invariant loads from the global address
783785  //  space.
784786  return  Subtarget.hasLDG () && CodeAddrSpace == NVPTX::AddressSpace::Global &&
@@ -810,6 +812,7 @@ static unsigned int getFenceOp(NVPTX::Ordering O, NVPTX::Scope S,
810812      return  T->hasMemoryOrdering () ? NVPTX::atomic_thread_fence_acquire_gpu
811813                                    : NVPTX::INT_MEMBAR_GL;
812814    case  NVPTX::Scope::Thread:
815+     case  NVPTX::Scope::DefaultDevice:
813816      report_fatal_error (
814817          formatv (" Unsupported scope \" {}\"  for acquire/release/acq_rel fence."  ,
815818                  ScopeToString (S)));
@@ -829,6 +832,7 @@ static unsigned int getFenceOp(NVPTX::Ordering O, NVPTX::Scope S,
829832      return  T->hasMemoryOrdering () ? NVPTX::atomic_thread_fence_release_gpu
830833                                    : NVPTX::INT_MEMBAR_GL;
831834    case  NVPTX::Scope::Thread:
835+     case  NVPTX::Scope::DefaultDevice:
832836      report_fatal_error (
833837          formatv (" Unsupported scope \" {}\"  for acquire/release/acq_rel fence."  ,
834838                  ScopeToString (S)));
@@ -848,6 +852,7 @@ static unsigned int getFenceOp(NVPTX::Ordering O, NVPTX::Scope S,
848852      return  T->hasMemoryOrdering () ? NVPTX::atomic_thread_fence_acq_rel_gpu
849853                                    : NVPTX::INT_MEMBAR_GL;
850854    case  NVPTX::Scope::Thread:
855+     case  NVPTX::Scope::DefaultDevice:
851856      report_fatal_error (
852857          formatv (" Unsupported scope \" {}\"  for acquire/release/acq_rel fence."  ,
853858                  ScopeToString (S)));
@@ -868,6 +873,7 @@ static unsigned int getFenceOp(NVPTX::Ordering O, NVPTX::Scope S,
868873      return  T->hasMemoryOrdering () ? NVPTX::atomic_thread_fence_seq_cst_gpu
869874                                    : NVPTX::INT_MEMBAR_GL;
870875    case  NVPTX::Scope::Thread:
876+     case  NVPTX::Scope::DefaultDevice:
871877      report_fatal_error (formatv (" Unsupported scope \" {}\"  for seq_cst fence."  ,
872878                                 ScopeToString (S)));
873879    }
@@ -1046,7 +1052,7 @@ bool NVPTXDAGToDAGISel::tryLoad(SDNode *N) {
10461052  const  MVT LoadedVT = LoadedEVT.getSimpleVT ();
10471053
10481054  //  Address Space Setting
1049-   const  unsigned  CodeAddrSpace = getAddrSpace (LD);
1055+   const  auto  CodeAddrSpace = getAddrSpace (LD);
10501056  if  (canLowerToLDG (*LD, *Subtarget, CodeAddrSpace))
10511057    return  tryLDG (LD);
10521058
@@ -1118,7 +1124,7 @@ bool NVPTXDAGToDAGISel::tryLoadVector(SDNode *N) {
11181124  const  MVT MemVT = MemEVT.getSimpleVT ();
11191125
11201126  //  Address Space Setting
1121-   const  unsigned  CodeAddrSpace = getAddrSpace (LD);
1127+   const  auto  CodeAddrSpace = getAddrSpace (LD);
11221128  if  (canLowerToLDG (*LD, *Subtarget, CodeAddrSpace))
11231129    return  tryLDG (LD);
11241130
@@ -1334,7 +1340,7 @@ bool NVPTXDAGToDAGISel::tryStore(SDNode *N) {
13341340    return  false ;
13351341
13361342  //  Address Space Setting
1337-   const  unsigned  CodeAddrSpace = getAddrSpace (ST);
1343+   const  auto  CodeAddrSpace = getAddrSpace (ST);
13381344
13391345  SDLoc DL (ST);
13401346  SDValue Chain = ST->getChain ();
@@ -1384,7 +1390,7 @@ bool NVPTXDAGToDAGISel::tryStoreVector(SDNode *N) {
13841390  assert (StoreVT.isSimple () && " Store value is not simple"  );
13851391
13861392  //  Address Space Setting
1387-   const  unsigned  CodeAddrSpace = getAddrSpace (ST);
1393+   const  auto  CodeAddrSpace = getAddrSpace (ST);
13881394  if  (CodeAddrSpace == NVPTX::AddressSpace::Const) {
13891395    report_fatal_error (" Cannot store to pointer that points to constant " 
13901396                       " memory space"  );
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