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[RISCV][NFC] Cleanup Negative Predicate Names (#155017)
Some negative predicates were named "Not Has <Ext>", and some were named "No <Ext>". I think the latter is clearer, so this moves those using the former to use the latter.
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lines changed

7 files changed

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-15
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llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -234,7 +234,7 @@ def FeatureStdExtZtso
234234
def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZtso()">,
235235
AssemblerPredicate<(all_of FeatureStdExtZtso),
236236
"'Ztso' (Memory Model - Total Store Order)">;
237-
def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;
237+
def NoStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;
238238

239239
def FeatureStdExtZa64rs
240240
: RISCVExtension<1, 0, "Reservation Set Size of at Most 64 Bytes">;
@@ -473,7 +473,7 @@ def FeatureStdExtZba
473473
def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">,
474474
AssemblerPredicate<(all_of FeatureStdExtZba),
475475
"'Zba' (Address Generation Instructions)">;
476-
def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">;
476+
def NoStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">;
477477

478478
def FeatureStdExtZbb
479479
: RISCVExtension<1, 0, "Basic Bit-Manipulation">,
@@ -1408,7 +1408,7 @@ def HasVendorXMIPSCBOP
14081408
: Predicate<"Subtarget->hasVendorXMIPSCBOP()">,
14091409
AssemblerPredicate<(all_of FeatureVendorXMIPSCBOP),
14101410
"'Xmipscbop' (MIPS hardware prefetch)">;
1411-
def NotHasVendorXMIPSCBOP : Predicate<"!Subtarget->hasVendorXMIPSCBOP()">;
1411+
def NoVendorXMIPSCBOP : Predicate<"!Subtarget->hasVendorXMIPSCBOP()">;
14121412

14131413
// WCH / Nanjing Qinheng Microelectronics Extension(s)
14141414

llvm/lib/Target/RISCV/RISCVGISel.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -147,7 +147,7 @@ def : Pat<(i32 (trunc GPR:$src)), (COPY GPR:$src)>;
147147
def : Pat<(zext_is_sext (i32 GPR:$src)), (ADDIW GPR:$src, 0)>;
148148
}
149149

150-
let Predicates = [IsRV64, NotHasStdExtZba] in
150+
let Predicates = [IsRV64, NoStdExtZba] in
151151
def : Pat<(zext (i32 GPR:$src)), (SRLI (i64 (SLLI GPR:$src, 32)), 32)>;
152152

153153
let Predicates = [IsRV32, NoStdExtZbb, NoStdExtZbkb] in

llvm/lib/Target/RISCV/RISCVInstrInfo.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2139,14 +2139,14 @@ def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
21392139

21402140
/// RV64 patterns
21412141

2142-
let Predicates = [IsRV64, NotHasStdExtZba] in {
2142+
let Predicates = [IsRV64, NoStdExtZba] in {
21432143
def : Pat<(i64 (and GPR:$rs1, 0xffffffff)), (SRLI (i64 (SLLI GPR:$rs1, 32)), 32)>;
21442144

21452145
// If we're shifting a 32-bit zero extended value left by 0-31 bits, use 2
21462146
// shifts instead of 3. This can occur when unsigned is used to index an array.
21472147
def : Pat<(i64 (shl (and GPR:$rs1, 0xffffffff), uimm5:$shamt)),
21482148
(SRLI (i64 (SLLI GPR:$rs1, 32)), (ImmSubFrom32 uimm5:$shamt))>;
2149-
}
2149+
} // Predicates = [IsRV64, NoStdExtZba]
21502150

21512151
class binop_allhusers<SDPatternOperator operator>
21522152
: PatFrag<(ops node:$lhs, node:$rhs),

llvm/lib/Target/RISCV/RISCVInstrInfoA.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -190,7 +190,7 @@ let Predicates = [HasAtomicLdSt, IsRV64] in {
190190

191191
multiclass AMOPat<string AtomicOp, string BaseInst, ValueType vt = XLenVT,
192192
list<Predicate> ExtraPreds = []> {
193-
let Predicates = !listconcat([HasStdExtA, NotHasStdExtZtso], ExtraPreds) in {
193+
let Predicates = !listconcat([HasStdExtA, NoStdExtZtso], ExtraPreds) in {
194194
def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_monotonic"),
195195
!cast<RVInst>(BaseInst), vt>;
196196
def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_acquire"),

llvm/lib/Target/RISCV/RISCVInstrInfoM.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -111,11 +111,11 @@ def : Pat<(srem (sexti32 (i64 GPR:$rs1)), (sexti32 (i64 GPR:$rs2))),
111111
(REMW GPR:$rs1, GPR:$rs2)>;
112112
} // Predicates = [HasStdExtM, IsRV64]
113113

114-
let Predicates = [HasStdExtZmmul, IsRV64, NotHasStdExtZba] in {
114+
let Predicates = [HasStdExtZmmul, IsRV64, NoStdExtZba] in {
115115
// Special case for calculating the full 64-bit product of a 32x32 unsigned
116116
// multiply where the inputs aren't known to be zero extended. We can shift the
117117
// inputs left by 32 and use a MULHU. This saves two SRLIs needed to finish
118118
// zeroing the upper 32 bits.
119119
def : Pat<(i64 (mul (and GPR:$rs1, 0xffffffff), (and GPR:$rs2, 0xffffffff))),
120120
(MULHU (i64 (SLLI GPR:$rs1, 32)), (i64 (SLLI GPR:$rs2, 32)))>;
121-
} // Predicates = [HasStdExtZmmul, IsRV64, NotHasStdExtZba]
121+
} // Predicates = [HasStdExtZmmul, IsRV64, NoStdExtZba]

llvm/lib/Target/RISCV/RISCVInstrInfoZa.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,7 @@ defm AMOCAS_Q : AMO_cas_aq_rl<0b00101, 0b100, "amocas.q", GPRPairRV64>;
7070

7171
multiclass AMOCASPat<string AtomicOp, string BaseInst, ValueType vt = XLenVT,
7272
list<Predicate> ExtraPreds = []> {
73-
let Predicates = !listconcat([HasStdExtZacas, NotHasStdExtZtso], ExtraPreds) in {
73+
let Predicates = !listconcat([HasStdExtZacas, NoStdExtZtso], ExtraPreds) in {
7474
def : Pat<(!cast<PatFrag>(AtomicOp#"_monotonic") (vt GPR:$addr),
7575
(vt GPR:$cmp),
7676
(vt GPR:$new)),
@@ -91,7 +91,7 @@ multiclass AMOCASPat<string AtomicOp, string BaseInst, ValueType vt = XLenVT,
9191
(vt GPR:$cmp),
9292
(vt GPR:$new)),
9393
(!cast<RVInst>(BaseInst#"_AQ_RL") GPR:$cmp, GPR:$addr, GPR:$new)>;
94-
} // Predicates = !listconcat([HasStdExtZacas, NotHasStdExtZtso], ExtraPreds)
94+
} // Predicates = !listconcat([HasStdExtZacas, NoStdExtZtso], ExtraPreds)
9595
let Predicates = !listconcat([HasStdExtZacas, HasStdExtZtso], ExtraPreds) in {
9696
def : Pat<(!cast<PatFrag>(AtomicOp#"_monotonic") (vt GPR:$addr),
9797
(vt GPR:$cmp),

llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -58,19 +58,19 @@ let Predicates = [HasStdExtZicboz] in {
5858
def CBO_ZERO : CBO_r<0b000000000100, "cbo.zero">, Sched<[]>;
5959
} // Predicates = [HasStdExtZicboz]
6060

61-
let Predicates = [HasStdExtZicbop, NotHasVendorXMIPSCBOP] in {
61+
let Predicates = [HasStdExtZicbop, NoVendorXMIPSCBOP] in {
6262
def PREFETCH_I : Prefetch_ri<0b00000, "prefetch.i">, Sched<[]>;
6363
def PREFETCH_R : Prefetch_ri<0b00001, "prefetch.r">, Sched<[]>;
6464
def PREFETCH_W : Prefetch_ri<0b00011, "prefetch.w">, Sched<[]>;
65-
} // Predicates = [HasStdExtZicbop]
65+
} // Predicates = [HasStdExtZicbop, NoVendorXMIPSCBOP]
6666

6767
//===----------------------------------------------------------------------===//
6868
// Patterns
6969
//===----------------------------------------------------------------------===//
7070

7171
def AddrRegImmLsb00000 : ComplexPattern<iPTR, 2, "SelectAddrRegImmLsb00000">;
7272

73-
let Predicates = [HasStdExtZicbop, NotHasVendorXMIPSCBOP] in {
73+
let Predicates = [HasStdExtZicbop, NoVendorXMIPSCBOP] in {
7474
def : Pat<(prefetch (AddrRegImmLsb00000 (XLenVT GPR:$rs1), simm12_lsb00000:$imm12),
7575
timm, timm, (i32 0)),
7676
(PREFETCH_I GPR:$rs1, simm12_lsb00000:$imm12)>;
@@ -80,4 +80,4 @@ let Predicates = [HasStdExtZicbop, NotHasVendorXMIPSCBOP] in {
8080
def : Pat<(prefetch (AddrRegImmLsb00000 (XLenVT GPR:$rs1), simm12_lsb00000:$imm12),
8181
(i32 1), timm, (i32 1)),
8282
(PREFETCH_W GPR:$rs1, simm12_lsb00000:$imm12)>;
83-
}
83+
} // Predicates = [HasStdExtZicbop, NoVendorXMIPSCBOP]

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