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1 parent 93b41b7 commit 67795f8Copy full SHA for 67795f8
llvm/test/MC/RISCV/rv64xtheadmempair-invalid.s
@@ -15,4 +15,5 @@ th.lwd a3, a4, (a5), 3, 5 # CHECK: [[@LINE]]:25: error: operand must be consta
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th.swd t3, t4, (t5), 5, 4 # CHECK: [[@LINE]]:22: error: immediate must be an integer in the range [0, 3]
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th.swd t3, t4, (t5) # CHECK: [[@LINE]]:1: error: too few operands for instruction
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th.swd t3, t4, (t5), 3, 5 # CHECK: [[@LINE]]:25: error: operand must be constant 3
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-th.lwud x6, x6, (x6), 2, 3 # CHECK: [[@LINE]]:9: error: rs1, rd1, and rd2 cannot all be the same
+th.ldd x6, x6, (x7), 2, 3 # CHECK: [[@LINE]]:8: error: rs1, rd1, and rd2 cannot overlap
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+th.lwud x6, x6, (x6), 2, 3 # CHECK: [[@LINE]]:9: error: rs1, rd1, and rd2 cannot overlap
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