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fix tests
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3 files changed

+86
-72
lines changed

3 files changed

+86
-72
lines changed

‎llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-concat.ll‎

Lines changed: 55 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -70,9 +70,12 @@ define <16 x i8> @concat_v16i8(<8 x i8> %op1, <8 x i8> %op2) {
7070
;
7171
; NONEON-NOSVE-LABEL: concat_v16i8:
7272
; NONEON-NOSVE: // %bb.0:
73-
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #-16]!
74-
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
75-
; NONEON-NOSVE-NEXT: ldr q0, [sp], #16
73+
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #-32]!
74+
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32
75+
; NONEON-NOSVE-NEXT: ldp x8, x9, [sp]
76+
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #16]
77+
; NONEON-NOSVE-NEXT: ldr q0, [sp, #16]
78+
; NONEON-NOSVE-NEXT: add sp, sp, #32
7679
; NONEON-NOSVE-NEXT: ret
7780
%res = shufflevector <8 x i8> %op1, <8 x i8> %op2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,
7881
i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -181,9 +184,12 @@ define <8 x i16> @concat_v8i16(<4 x i16> %op1, <4 x i16> %op2) {
181184
;
182185
; NONEON-NOSVE-LABEL: concat_v8i16:
183186
; NONEON-NOSVE: // %bb.0:
184-
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #-16]!
185-
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
186-
; NONEON-NOSVE-NEXT: ldr q0, [sp], #16
187+
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #-32]!
188+
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32
189+
; NONEON-NOSVE-NEXT: ldp x8, x9, [sp]
190+
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #16]
191+
; NONEON-NOSVE-NEXT: ldr q0, [sp, #16]
192+
; NONEON-NOSVE-NEXT: add sp, sp, #32
187193
; NONEON-NOSVE-NEXT: ret
188194
%res = shufflevector <4 x i16> %op1, <4 x i16> %op2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
189195
ret <8 x i16> %res
@@ -279,9 +285,14 @@ define <4 x i32> @concat_v4i32(<2 x i32> %op1, <2 x i32> %op2) {
279285
;
280286
; NONEON-NOSVE-LABEL: concat_v4i32:
281287
; NONEON-NOSVE: // %bb.0:
282-
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #-16]!
283-
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
284-
; NONEON-NOSVE-NEXT: ldr q0, [sp], #16
288+
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #-32]!
289+
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32
290+
; NONEON-NOSVE-NEXT: ldp w8, w9, [sp, #8]
291+
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #24]
292+
; NONEON-NOSVE-NEXT: ldp w8, w9, [sp]
293+
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #16]
294+
; NONEON-NOSVE-NEXT: ldr q0, [sp, #16]
295+
; NONEON-NOSVE-NEXT: add sp, sp, #32
285296
; NONEON-NOSVE-NEXT: ret
286297
%res = shufflevector <2 x i32> %op1, <2 x i32> %op2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
287298
ret <4 x i32> %res
@@ -441,9 +452,12 @@ define <8 x half> @concat_v8f16(<4 x half> %op1, <4 x half> %op2) {
441452
;
442453
; NONEON-NOSVE-LABEL: concat_v8f16:
443454
; NONEON-NOSVE: // %bb.0:
444-
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #-16]!
445-
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
446-
; NONEON-NOSVE-NEXT: ldr q0, [sp], #16
455+
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #-32]!
456+
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32
457+
; NONEON-NOSVE-NEXT: ldp x8, x9, [sp]
458+
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #16]
459+
; NONEON-NOSVE-NEXT: ldr q0, [sp, #16]
460+
; NONEON-NOSVE-NEXT: add sp, sp, #32
447461
; NONEON-NOSVE-NEXT: ret
448462
%res = shufflevector <4 x half> %op1, <4 x half> %op2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
449463
ret <8 x half> %res
@@ -539,9 +553,14 @@ define <4 x float> @concat_v4f32(<2 x float> %op1, <2 x float> %op2) {
539553
;
540554
; NONEON-NOSVE-LABEL: concat_v4f32:
541555
; NONEON-NOSVE: // %bb.0:
542-
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #-16]!
543-
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
544-
; NONEON-NOSVE-NEXT: ldr q0, [sp], #16
556+
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #-32]!
557+
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32
558+
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #8]
559+
; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #24]
560+
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp]
561+
; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #16]
562+
; NONEON-NOSVE-NEXT: ldr q0, [sp, #16]
563+
; NONEON-NOSVE-NEXT: add sp, sp, #32
545564
; NONEON-NOSVE-NEXT: ret
546565
%res = shufflevector <2 x float> %op1, <2 x float> %op2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
547566
ret <4 x float> %res
@@ -754,12 +773,15 @@ define void @concat_v32i8_4op(ptr %a, ptr %b) {
754773
;
755774
; NONEON-NOSVE-LABEL: concat_v32i8_4op:
756775
; NONEON-NOSVE: // %bb.0:
776+
; NONEON-NOSVE-NEXT: sub sp, sp, #32
777+
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32
757778
; NONEON-NOSVE-NEXT: ldr d0, [x0]
758-
; NONEON-NOSVE-NEXT: str d0, [sp, #-16]!
759-
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
760-
; NONEON-NOSVE-NEXT: ldr q0, [sp]
779+
; NONEON-NOSVE-NEXT: str d0, [sp, #8]
780+
; NONEON-NOSVE-NEXT: ldr x8, [sp, #8]
781+
; NONEON-NOSVE-NEXT: str x8, [sp, #16]
782+
; NONEON-NOSVE-NEXT: ldr q0, [sp, #16]
761783
; NONEON-NOSVE-NEXT: str q0, [x1]
762-
; NONEON-NOSVE-NEXT: add sp, sp, #16
784+
; NONEON-NOSVE-NEXT: add sp, sp, #32
763785
; NONEON-NOSVE-NEXT: ret
764786
%op1 = load <8 x i8>, ptr %a
765787
%shuffle = shufflevector <8 x i8> %op1, <8 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,
@@ -781,12 +803,15 @@ define void @concat_v16i16_4op(ptr %a, ptr %b) {
781803
;
782804
; NONEON-NOSVE-LABEL: concat_v16i16_4op:
783805
; NONEON-NOSVE: // %bb.0:
806+
; NONEON-NOSVE-NEXT: sub sp, sp, #32
807+
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32
784808
; NONEON-NOSVE-NEXT: ldr d0, [x0]
785-
; NONEON-NOSVE-NEXT: str d0, [sp, #-16]!
786-
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
787-
; NONEON-NOSVE-NEXT: ldr q0, [sp]
809+
; NONEON-NOSVE-NEXT: str d0, [sp, #8]
810+
; NONEON-NOSVE-NEXT: ldr x8, [sp, #8]
811+
; NONEON-NOSVE-NEXT: str x8, [sp, #16]
812+
; NONEON-NOSVE-NEXT: ldr q0, [sp, #16]
788813
; NONEON-NOSVE-NEXT: str q0, [x1]
789-
; NONEON-NOSVE-NEXT: add sp, sp, #16
814+
; NONEON-NOSVE-NEXT: add sp, sp, #32
790815
; NONEON-NOSVE-NEXT: ret
791816
%op1 = load <4 x i16>, ptr %a
792817
%shuffle = shufflevector <4 x i16> %op1, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
@@ -805,12 +830,15 @@ define void @concat_v8i32_4op(ptr %a, ptr %b) {
805830
;
806831
; NONEON-NOSVE-LABEL: concat_v8i32_4op:
807832
; NONEON-NOSVE: // %bb.0:
833+
; NONEON-NOSVE-NEXT: sub sp, sp, #32
834+
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32
808835
; NONEON-NOSVE-NEXT: ldr d0, [x0]
809-
; NONEON-NOSVE-NEXT: str d0, [sp, #-16]!
810-
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
811-
; NONEON-NOSVE-NEXT: ldr q0, [sp]
836+
; NONEON-NOSVE-NEXT: str d0, [sp, #8]
837+
; NONEON-NOSVE-NEXT: ldp w8, w9, [sp, #8]
838+
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #16]
839+
; NONEON-NOSVE-NEXT: ldr q0, [sp, #16]
812840
; NONEON-NOSVE-NEXT: str q0, [x1]
813-
; NONEON-NOSVE-NEXT: add sp, sp, #16
841+
; NONEON-NOSVE-NEXT: add sp, sp, #32
814842
; NONEON-NOSVE-NEXT: ret
815843
%op1 = load <2 x i32>, ptr %a
816844
%shuffle = shufflevector <2 x i32> %op1, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>

‎llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll‎

Lines changed: 30 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -1138,17 +1138,15 @@ define <2 x i64> @smulh_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
11381138
;
11391139
; NONEON-NOSVE-LABEL: smulh_v2i64:
11401140
; NONEON-NOSVE: // %bb.0:
1141-
; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-64]!
1141+
; NONEON-NOSVE-NEXT: sub sp, sp, #64
11421142
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 64
1143-
; NONEON-NOSVE-NEXT: ldp x9, x8, [sp]
1144-
; NONEON-NOSVE-NEXT: ldp x11, x10, [sp, #16]
1143+
; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #16]
1144+
; NONEON-NOSVE-NEXT: ldp x9, x8, [sp, #16]
1145+
; NONEON-NOSVE-NEXT: ldp x11, x10, [sp, #32]
11451146
; NONEON-NOSVE-NEXT: smulh x8, x8, x10
11461147
; NONEON-NOSVE-NEXT: smulh x9, x9, x11
1147-
; NONEON-NOSVE-NEXT: stp x9, x8, [sp, #32]
1148-
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #32]
1149-
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #48]
1150-
; NONEON-NOSVE-NEXT: ldr q0, [sp, #48]
1151-
; NONEON-NOSVE-NEXT: add sp, sp, #64
1148+
; NONEON-NOSVE-NEXT: stp x9, x8, [sp]
1149+
; NONEON-NOSVE-NEXT: ldr q0, [sp], #64
11521150
; NONEON-NOSVE-NEXT: ret
11531151
%1 = sext <2 x i64> %op1 to <2 x i128>
11541152
%2 = sext <2 x i64> %op2 to <2 x i128>
@@ -1185,23 +1183,19 @@ define void @smulh_v4i64(ptr %a, ptr %b) {
11851183
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 128
11861184
; NONEON-NOSVE-NEXT: ldp q1, q0, [x0]
11871185
; NONEON-NOSVE-NEXT: ldp q2, q3, [x1]
1188-
; NONEON-NOSVE-NEXT: stp q1, q2, [sp]
1189-
; NONEON-NOSVE-NEXT: ldp x11, x10, [sp]
1190-
; NONEON-NOSVE-NEXT: stp q0, q3, [sp, #32]
1191-
; NONEON-NOSVE-NEXT: ldp x13, x12, [sp, #16]
1192-
; NONEON-NOSVE-NEXT: ldp x9, x8, [sp, #32]
1186+
; NONEON-NOSVE-NEXT: stp q1, q2, [sp, #32]
1187+
; NONEON-NOSVE-NEXT: ldp x11, x10, [sp, #32]
1188+
; NONEON-NOSVE-NEXT: stp q0, q3, [sp, #64]
1189+
; NONEON-NOSVE-NEXT: ldp x13, x12, [sp, #48]
1190+
; NONEON-NOSVE-NEXT: ldp x9, x8, [sp, #64]
11931191
; NONEON-NOSVE-NEXT: smulh x10, x10, x12
1194-
; NONEON-NOSVE-NEXT: ldp x14, x12, [sp, #48]
1192+
; NONEON-NOSVE-NEXT: ldp x14, x12, [sp, #80]
11951193
; NONEON-NOSVE-NEXT: smulh x11, x11, x13
11961194
; NONEON-NOSVE-NEXT: smulh x8, x8, x12
11971195
; NONEON-NOSVE-NEXT: smulh x9, x9, x14
1198-
; NONEON-NOSVE-NEXT: stp x11, x10, [sp, #64]
1199-
; NONEON-NOSVE-NEXT: stp x9, x8, [sp, #80]
1200-
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #80]
1201-
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #112]
1202-
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #64]
1203-
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #96]
1204-
; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #96]
1196+
; NONEON-NOSVE-NEXT: stp x11, x10, [sp, #16]
1197+
; NONEON-NOSVE-NEXT: stp x9, x8, [sp]
1198+
; NONEON-NOSVE-NEXT: ldp q1, q0, [sp]
12051199
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
12061200
; NONEON-NOSVE-NEXT: add sp, sp, #128
12071201
; NONEON-NOSVE-NEXT: ret
@@ -2339,17 +2333,15 @@ define <2 x i64> @umulh_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
23392333
;
23402334
; NONEON-NOSVE-LABEL: umulh_v2i64:
23412335
; NONEON-NOSVE: // %bb.0:
2342-
; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-64]!
2336+
; NONEON-NOSVE-NEXT: sub sp, sp, #64
23432337
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 64
2344-
; NONEON-NOSVE-NEXT: ldp x9, x8, [sp]
2345-
; NONEON-NOSVE-NEXT: ldp x11, x10, [sp, #16]
2338+
; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #16]
2339+
; NONEON-NOSVE-NEXT: ldp x9, x8, [sp, #16]
2340+
; NONEON-NOSVE-NEXT: ldp x11, x10, [sp, #32]
23462341
; NONEON-NOSVE-NEXT: umulh x8, x8, x10
23472342
; NONEON-NOSVE-NEXT: umulh x9, x9, x11
2348-
; NONEON-NOSVE-NEXT: stp x9, x8, [sp, #32]
2349-
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #32]
2350-
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #48]
2351-
; NONEON-NOSVE-NEXT: ldr q0, [sp, #48]
2352-
; NONEON-NOSVE-NEXT: add sp, sp, #64
2343+
; NONEON-NOSVE-NEXT: stp x9, x8, [sp]
2344+
; NONEON-NOSVE-NEXT: ldr q0, [sp], #64
23532345
; NONEON-NOSVE-NEXT: ret
23542346
%1 = zext <2 x i64> %op1 to <2 x i128>
23552347
%2 = zext <2 x i64> %op2 to <2 x i128>
@@ -2386,23 +2378,19 @@ define void @umulh_v4i64(ptr %a, ptr %b) {
23862378
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 128
23872379
; NONEON-NOSVE-NEXT: ldp q1, q0, [x0]
23882380
; NONEON-NOSVE-NEXT: ldp q2, q3, [x1]
2389-
; NONEON-NOSVE-NEXT: stp q1, q2, [sp]
2390-
; NONEON-NOSVE-NEXT: ldp x11, x10, [sp]
2391-
; NONEON-NOSVE-NEXT: stp q0, q3, [sp, #32]
2392-
; NONEON-NOSVE-NEXT: ldp x13, x12, [sp, #16]
2393-
; NONEON-NOSVE-NEXT: ldp x9, x8, [sp, #32]
2381+
; NONEON-NOSVE-NEXT: stp q1, q2, [sp, #32]
2382+
; NONEON-NOSVE-NEXT: ldp x11, x10, [sp, #32]
2383+
; NONEON-NOSVE-NEXT: stp q0, q3, [sp, #64]
2384+
; NONEON-NOSVE-NEXT: ldp x13, x12, [sp, #48]
2385+
; NONEON-NOSVE-NEXT: ldp x9, x8, [sp, #64]
23942386
; NONEON-NOSVE-NEXT: umulh x10, x10, x12
2395-
; NONEON-NOSVE-NEXT: ldp x14, x12, [sp, #48]
2387+
; NONEON-NOSVE-NEXT: ldp x14, x12, [sp, #80]
23962388
; NONEON-NOSVE-NEXT: umulh x11, x11, x13
23972389
; NONEON-NOSVE-NEXT: umulh x8, x8, x12
23982390
; NONEON-NOSVE-NEXT: umulh x9, x9, x14
2399-
; NONEON-NOSVE-NEXT: stp x11, x10, [sp, #64]
2400-
; NONEON-NOSVE-NEXT: stp x9, x8, [sp, #80]
2401-
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #80]
2402-
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #112]
2403-
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #64]
2404-
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #96]
2405-
; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #96]
2391+
; NONEON-NOSVE-NEXT: stp x11, x10, [sp, #16]
2392+
; NONEON-NOSVE-NEXT: stp x9, x8, [sp]
2393+
; NONEON-NOSVE-NEXT: ldp q1, q0, [sp]
24062394
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
24072395
; NONEON-NOSVE-NEXT: add sp, sp, #128
24082396
; NONEON-NOSVE-NEXT: ret

‎llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc-stores.ll‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -142,9 +142,7 @@ define void @store_trunc_v2i256i64(ptr %ap, ptr %dest) {
142142
; NONEON-NOSVE-NEXT: ldr x9, [x0]
143143
; NONEON-NOSVE-NEXT: stp x9, x8, [sp, #-32]!
144144
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32
145-
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp]
146-
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #16]
147-
; NONEON-NOSVE-NEXT: ldr q0, [sp, #16]
145+
; NONEON-NOSVE-NEXT: ldr q0, [sp]
148146
; NONEON-NOSVE-NEXT: str q0, [x1]
149147
; NONEON-NOSVE-NEXT: add sp, sp, #32
150148
; NONEON-NOSVE-NEXT: ret

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