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llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp

Lines changed: 29 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -725,7 +725,7 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
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// We have some custom DAG combine patterns for these nodes
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setTargetDAGCombine({ISD::ADD, ISD::AND, ISD::EXTRACT_VECTOR_ELT, ISD::FADD,
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ISD::LOAD, ISD::MUL, ISD::SHL, ISD::SREM, ISD::UREM,
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ISD::VSELECT});
728+
ISD::VSELECT, ISD::SELECT});
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// setcc for f16x2 and bf16x2 needs special handling to prevent
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// legalizer's attempt to scalarize it due to v2i1 not being legal.
@@ -5999,6 +5999,32 @@ static SDValue PerformLOADCombine(SDNode *N,
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DL);
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}
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// This transformations was once reliably performed by instcombine, but thanks
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// to poison semantics they are no longer safe for LLVM IR, perform them here
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// instead.
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static SDValue PerformSELECTCombine(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI) {
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return SDValue();
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if (!(N->getValueType(0) == MVT::i1))
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return SDValue();
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unsigned Opcode = N->getOpcode();
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SDValue SecondOperand;
6013+
if (auto Const = dyn_cast<ConstantSDNode>(N->getOperand(2)); Const && Const->isZero()) {
6014+
// (select cond, x, false) -> (and cond, x)
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Opcode = ISD::AND;
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SecondOperand = N->getOperand(1);
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} else if (auto Const = dyn_cast<ConstantSDNode>(N->getOperand(1)); Const && Const->isOne()) {
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// (select cond, true, x) -> (or cond, x)
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Opcode = ISD::OR;
6020+
SecondOperand = N->getOperand(2);
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} else {
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return SDValue();
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}
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return DCI.DAG.getNode(Opcode, SDLoc(N), MVT::i1, N->getOperand(0), SecondOperand);
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}
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SDValue NVPTXTargetLowering::PerformDAGCombine(SDNode *N,
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DAGCombinerInfo &DCI) const {
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CodeGenOptLevel OptLevel = getTargetMachine().getOptLevel();
@@ -6021,6 +6047,8 @@ SDValue NVPTXTargetLowering::PerformDAGCombine(SDNode *N,
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return PerformSETCCCombine(N, DCI, STI.getSmVersion());
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case ISD::LOAD:
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return PerformLOADCombine(N, DCI);
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case ISD::SELECT:
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return PerformSELECTCombine(N, DCI);
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case NVPTXISD::StoreRetval:
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case NVPTXISD::StoreRetvalV2:
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case NVPTXISD::StoreRetvalV4:

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