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[SelectionDAG] Fix assertion failure on inline asm register type mismatch
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3 files changed

+33
-1
lines changed

3 files changed

+33
-1
lines changed

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -365,7 +365,17 @@ static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
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assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
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NumParts = NumRegs; // Silence a compiler warning.
368-
assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
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// Check if the register type matches the part type
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if (RegisterVT != PartVT) {
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diagnosePossiblyInvalidConstraint(
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*DAG.getContext(), V,
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"register type (" + EVT(RegisterVT).getEVTString() +
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") doesn't match operand type (" + EVT(PartVT).getEVTString() +
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")");
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return DAG.getUNDEF(ValueVT);
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}
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assert(RegisterVT.getSizeInBits() ==
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Parts[0].getSimpleValueType().getSizeInBits() &&
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"Part type sizes don't match!");

llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -61825,6 +61825,8 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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break;
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case 'y': // MMX_REGS if MMX allowed.
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if (!Subtarget.hasMMX()) break;
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// MMX registers are 64-bit only
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if (VT.getSizeInBits() != 64) break;
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return std::make_pair(0U, &X86::VR64RegClass);
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case 'v':
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case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,20 @@
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; RUN: not llc -mtriple=x86_64-unknown-linux-gnu < %s 2>&1 | FileCheck %s
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; Test that using MMX register constraint 'y' (64-bit) with a 256-bit vector
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; produces a proper error message instead of an assertion failure.
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; CHECK: error: couldn't allocate output register for constraint 'y'
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define <8 x i32> @test_mmx_constraint_size_mismatch() {
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entry:
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%out = tail call <8 x i32> asm "something $0", "=y"()
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ret <8 x i32> %out
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}
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; Also test with a different vector size
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define <4 x i32> @test_mmx_constraint_128bit() {
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entry:
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%out = tail call <4 x i32> asm "something $0", "=y"()
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ret <4 x i32> %out
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}
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