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3 files changed

+32
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‎llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -9897,18 +9897,17 @@ SDValue TargetLowering::expandBSWAP(SDNode *N, SelectionDAG &DAG) const {
98979897
return SDValue();
98989898
case MVT::i16:
98999899
// Use a rotate by 8. This can be further expanded if necessary.
9900-
return DAG.getNode(ISD::ROTR, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
9900+
return DAG.getNode(ISD::ROTL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
99019901
case MVT::i32:
99029902
if (isOperationLegal(ISD::ROTR, VT)) {
9903+
SDValue Mask = DAG.getConstant(0x00FF00FF, dl, VT);
99039904
// (x & 0x00FF00FF) rotr 8 | (x rotl 8) & 0x00FF00FF
9904-
SDValue And = DAG.getNode(ISD::AND, dl, VT, Op,
9905-
DAG.getConstant(0x00FF00FF, dl, VT));
9905+
SDValue And = DAG.getNode(ISD::AND, dl, VT, Op, Mask);
99069906
SDValue Rotr =
99079907
DAG.getNode(ISD::ROTR, dl, VT, And, DAG.getConstant(8, dl, SHVT));
99089908
SDValue Rotl =
99099909
DAG.getNode(ISD::ROTL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
9910-
SDValue And2 = DAG.getNode(ISD::AND, dl, VT, Rotl,
9911-
DAG.getConstant(0x00FF00FF, dl, VT));
9910+
SDValue And2 = DAG.getNode(ISD::AND, dl, VT, Rotl, Mask);
99129911
return DAG.getNode(ISD::OR, dl, VT, Rotr, And2);
99139912
}
99149913
Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));

‎llvm/test/CodeGen/ARM/load-combine-big-endian.ll‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -57,8 +57,8 @@ define i32 @load_i32_by_i8_bswap(ptr %arg) {
5757
; CHECK-NEXT: ldr r0, [r0]
5858
; CHECK-NEXT: orr r1, r1, #16711680
5959
; CHECK-NEXT: and r2, r0, r1
60-
; CHECK-NEXT: and r0, r1, r0, lsr #8
61-
; CHECK-NEXT: orr r0, r0, r2, ror #24
60+
; CHECK-NEXT: and r0, r1, r0, ror #24
61+
; CHECK-NEXT: orr r0, r0, r2, ror #8
6262
; CHECK-NEXT: mov pc, lr
6363
;
6464
; CHECK-ARMv6-LABEL: load_i32_by_i8_bswap:
@@ -226,11 +226,11 @@ define i64 @load_i64_by_i8_bswap(ptr %arg) {
226226
; CHECK-NEXT: ldr r0, [r0, #4]
227227
; CHECK-NEXT: orr r2, r2, #16711680
228228
; CHECK-NEXT: and r3, r0, r2
229-
; CHECK-NEXT: and r0, r2, r0, lsr #8
230-
; CHECK-NEXT: orr r0, r0, r3, ror #24
229+
; CHECK-NEXT: and r0, r2, r0, ror #24
230+
; CHECK-NEXT: orr r0, r0, r3, ror #8
231231
; CHECK-NEXT: and r3, r1, r2
232-
; CHECK-NEXT: and r1, r2, r1, lsr #8
233-
; CHECK-NEXT: orr r1, r1, r3, ror #24
232+
; CHECK-NEXT: and r1, r2, r1, ror #24
233+
; CHECK-NEXT: orr r1, r1, r3, ror #8
234234
; CHECK-NEXT: mov pc, lr
235235
;
236236
; CHECK-ARMv6-LABEL: load_i64_by_i8_bswap:
@@ -374,8 +374,8 @@ define i32 @load_i32_by_i8_nonzero_offset(ptr %arg) {
374374
; CHECK-NEXT: ldr r0, [r0, #1]
375375
; CHECK-NEXT: orr r1, r1, #16711680
376376
; CHECK-NEXT: and r2, r0, r1
377-
; CHECK-NEXT: and r0, r1, r0, lsr #8
378-
; CHECK-NEXT: orr r0, r0, r2, ror #24
377+
; CHECK-NEXT: and r0, r1, r0, ror #24
378+
; CHECK-NEXT: orr r0, r0, r2, ror #8
379379
; CHECK-NEXT: mov pc, lr
380380
;
381381
; CHECK-ARMv6-LABEL: load_i32_by_i8_nonzero_offset:
@@ -429,8 +429,8 @@ define i32 @load_i32_by_i8_neg_offset(ptr %arg) {
429429
; CHECK-NEXT: ldr r0, [r0, #-4]
430430
; CHECK-NEXT: orr r1, r1, #16711680
431431
; CHECK-NEXT: and r2, r0, r1
432-
; CHECK-NEXT: and r0, r1, r0, lsr #8
433-
; CHECK-NEXT: orr r0, r0, r2, ror #24
432+
; CHECK-NEXT: and r0, r1, r0, ror #24
433+
; CHECK-NEXT: orr r0, r0, r2, ror #8
434434
; CHECK-NEXT: mov pc, lr
435435
;
436436
; CHECK-ARMv6-LABEL: load_i32_by_i8_neg_offset:
@@ -580,8 +580,8 @@ define i32 @load_i32_by_bswap_i16(ptr %arg) {
580580
; CHECK-NEXT: ldr r0, [r0]
581581
; CHECK-NEXT: orr r1, r1, #16711680
582582
; CHECK-NEXT: and r2, r0, r1
583-
; CHECK-NEXT: and r0, r1, r0, lsr #8
584-
; CHECK-NEXT: orr r0, r0, r2, ror #24
583+
; CHECK-NEXT: and r0, r1, r0, ror #24
584+
; CHECK-NEXT: orr r0, r0, r2, ror #8
585585
; CHECK-NEXT: mov pc, lr
586586
;
587587
; CHECK-ARMv6-LABEL: load_i32_by_bswap_i16:
@@ -658,8 +658,8 @@ define i32 @load_i32_by_i8_base_offset_index(ptr %arg, i32 %i) {
658658
; CHECK-NEXT: orr r1, r1, #16711680
659659
; CHECK-NEXT: ldr r0, [r0, #12]
660660
; CHECK-NEXT: and r2, r0, r1
661-
; CHECK-NEXT: and r0, r1, r0, lsr #8
662-
; CHECK-NEXT: orr r0, r0, r2, ror #24
661+
; CHECK-NEXT: and r0, r1, r0, ror #24
662+
; CHECK-NEXT: orr r0, r0, r2, ror #8
663663
; CHECK-NEXT: mov pc, lr
664664
;
665665
; CHECK-ARMv6-LABEL: load_i32_by_i8_base_offset_index:
@@ -722,8 +722,8 @@ define i32 @load_i32_by_i8_base_offset_index_2(ptr %arg, i32 %i) {
722722
; CHECK-NEXT: orr r1, r1, #16711680
723723
; CHECK-NEXT: ldr r0, [r0, #13]
724724
; CHECK-NEXT: and r2, r0, r1
725-
; CHECK-NEXT: and r0, r1, r0, lsr #8
726-
; CHECK-NEXT: orr r0, r0, r2, ror #24
725+
; CHECK-NEXT: and r0, r1, r0, ror #24
726+
; CHECK-NEXT: orr r0, r0, r2, ror #8
727727
; CHECK-NEXT: mov pc, lr
728728
;
729729
; CHECK-ARMv6-LABEL: load_i32_by_i8_base_offset_index_2:

‎llvm/test/CodeGen/ARM/load-combine.ll‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -121,8 +121,8 @@ define i32 @load_i32_by_i8_bswap(ptr %arg) {
121121
; CHECK-NEXT: ldr r0, [r0]
122122
; CHECK-NEXT: orr r1, r1, #16711680
123123
; CHECK-NEXT: and r2, r0, r1
124-
; CHECK-NEXT: and r0, r1, r0, lsr #8
125-
; CHECK-NEXT: orr r0, r0, r2, ror #24
124+
; CHECK-NEXT: and r0, r1, r0, ror #24
125+
; CHECK-NEXT: orr r0, r0, r2, ror #8
126126
; CHECK-NEXT: mov pc, lr
127127
;
128128
; CHECK-ARMv6-LABEL: load_i32_by_i8_bswap:
@@ -240,11 +240,11 @@ define i64 @load_i64_by_i8_bswap(ptr %arg) {
240240
; CHECK-NEXT: ldr r0, [r0, #4]
241241
; CHECK-NEXT: orr r2, r2, #16711680
242242
; CHECK-NEXT: and r3, r0, r2
243-
; CHECK-NEXT: and r0, r2, r0, lsr #8
244-
; CHECK-NEXT: orr r0, r0, r3, ror #24
243+
; CHECK-NEXT: and r0, r2, r0, ror #24
244+
; CHECK-NEXT: orr r0, r0, r3, ror #8
245245
; CHECK-NEXT: and r3, r1, r2
246-
; CHECK-NEXT: and r1, r2, r1, lsr #8
247-
; CHECK-NEXT: orr r1, r1, r3, ror #24
246+
; CHECK-NEXT: and r1, r2, r1, ror #24
247+
; CHECK-NEXT: orr r1, r1, r3, ror #8
248248
; CHECK-NEXT: mov pc, lr
249249
;
250250
; CHECK-ARMv6-LABEL: load_i64_by_i8_bswap:
@@ -410,8 +410,8 @@ define i32 @load_i32_by_i8_nonzero_offset_bswap(ptr %arg) {
410410
; CHECK-NEXT: ldr r0, [r0, #1]
411411
; CHECK-NEXT: orr r1, r1, #16711680
412412
; CHECK-NEXT: and r2, r0, r1
413-
; CHECK-NEXT: and r0, r1, r0, lsr #8
414-
; CHECK-NEXT: orr r0, r0, r2, ror #24
413+
; CHECK-NEXT: and r0, r1, r0, ror #24
414+
; CHECK-NEXT: orr r0, r0, r2, ror #8
415415
; CHECK-NEXT: mov pc, lr
416416
;
417417
; CHECK-ARMv6-LABEL: load_i32_by_i8_nonzero_offset_bswap:
@@ -464,8 +464,8 @@ define i32 @load_i32_by_i8_neg_offset_bswap(ptr %arg) {
464464
; CHECK-NEXT: ldr r0, [r0, #-4]
465465
; CHECK-NEXT: orr r1, r1, #16711680
466466
; CHECK-NEXT: and r2, r0, r1
467-
; CHECK-NEXT: and r0, r1, r0, lsr #8
468-
; CHECK-NEXT: orr r0, r0, r2, ror #24
467+
; CHECK-NEXT: and r0, r1, r0, ror #24
468+
; CHECK-NEXT: orr r0, r0, r2, ror #8
469469
; CHECK-NEXT: mov pc, lr
470470
;
471471
; CHECK-ARMv6-LABEL: load_i32_by_i8_neg_offset_bswap:
@@ -520,8 +520,8 @@ define i32 @load_i32_by_bswap_i16(ptr %arg) {
520520
; CHECK-NEXT: ldr r0, [r0]
521521
; CHECK-NEXT: orr r1, r1, #16711680
522522
; CHECK-NEXT: and r2, r0, r1
523-
; CHECK-NEXT: and r0, r1, r0, lsr #8
524-
; CHECK-NEXT: orr r0, r0, r2, ror #24
523+
; CHECK-NEXT: and r0, r1, r0, ror #24
524+
; CHECK-NEXT: orr r0, r0, r2, ror #8
525525
; CHECK-NEXT: mov pc, lr
526526
;
527527
; CHECK-ARMv6-LABEL: load_i32_by_bswap_i16:

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