Skip to content

Commit 68955ba

Browse files
committed
getregclassfor add t16
1 parent b5e70d0 commit 68955ba

File tree

1 file changed

+2
-0
lines changed

1 file changed

+2
-0
lines changed

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16965,6 +16965,8 @@ SITargetLowering::getRegClassFor(MVT VT, bool isDivergent) const {
1696516965
if (RC == &AMDGPU::VReg_1RegClass && !isDivergent)
1696616966
return Subtarget->isWave64() ? &AMDGPU::SReg_64RegClass
1696716967
: &AMDGPU::SReg_32RegClass;
16968+
if (VT == MVT::f16 && TRI->isVGPRClass(RC))
16969+
return RC;
1696816970
if (!TRI->isSGPRClass(RC) && !isDivergent)
1696916971
return TRI->getEquivalentSGPRClass(RC);
1697016972
if (TRI->isSGPRClass(RC) && isDivergent)

0 commit comments

Comments
 (0)