nit

Pierre-vh · Pierre-vh · commit 6900721fdec7 · 2025-11-17T10:05:14.000+01:00
diff --git a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
@@ -1249,7 +1249,7 @@ bool SIGfx6CacheControl::insertWait(MachineBasicBlock::iterator &MI,
 static bool canUseBUFFER_WBINVL1_VOL(const GCNSubtarget &ST) {
   if (ST.getGeneration() <= AMDGPUSubtarget::SOUTHERN_ISLANDS)
     return false;
-  return !(ST.isAmdPalOS() || ST.isMesa3DOS());
+  return !ST.isAmdPalOS() && !ST.isMesa3DOS();
 }
 
 bool SIGfx6CacheControl::insertAcquire(MachineBasicBlock::iterator &MI,

Original file line number	Diff line number	Diff line change
`@@ -1249,7 +1249,7 @@ bool SIGfx6CacheControl::insertWait(MachineBasicBlock::iterator &MI,`
`1249`	`1249`	`static bool canUseBUFFER_WBINVL1_VOL(const GCNSubtarget &ST) {`
`1250`	`1250`	`if (ST.getGeneration() <= AMDGPUSubtarget::SOUTHERN_ISLANDS)`
`1251`	`1251`	`return false;`
`1252`		`- return !(ST.isAmdPalOS() \|\| ST.isMesa3DOS());`
	`1252`	`+ return !ST.isAmdPalOS() && !ST.isMesa3DOS();`
`1253`	`1253`	`}`
`1254`	`1254`
`1255`	`1255`	`bool SIGfx6CacheControl::insertAcquire(MachineBasicBlock::iterator &MI,`