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4vtomat4vtomat
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fixup! update test
1 parent fe67c22 commit 696bad8

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-44
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2 files changed

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‎llvm/test/CodeGen/RISCV/zilsd-ldst-opt-prera.mir‎

Lines changed: 42 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -262,8 +262,8 @@ body: |
262262
; CHECK-4BYTE: liveins: $x10
263263
; CHECK-4BYTE-NEXT: {{ $}}
264264
; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
265-
; CHECK-4BYTE-NEXT: early-clobber %1:gpr, %2:gpr = PseudoLD_RV32_OPT [[COPY]], 0 :: (load (s32))
266-
; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD %1, %2
265+
; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 0 :: (load (s32))
266+
; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT1]]
267267
; CHECK-4BYTE-NEXT: PseudoRET
268268
%0:gpr = COPY $x10
269269
%1:gpr = LW %0, 0 :: (load (s32))
@@ -325,16 +325,16 @@ body: |
325325
; CHECK: liveins: $x10
326326
; CHECK-NEXT: {{ $}}
327327
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
328-
; CHECK-NEXT: early-clobber %1:gpr, %2:gpr = PseudoLD_RV32_OPT [[COPY]], 0 :: (load (s32), align 8), (load (s32))
329-
; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD %1, %2
328+
; CHECK-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 0 :: (load (s32), align 8), (load (s32))
329+
; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT1]]
330330
; CHECK-NEXT: PseudoRET
331331
;
332332
; CHECK-4BYTE-LABEL: name: basic_load_combine_8_byte_aligned
333333
; CHECK-4BYTE: liveins: $x10
334334
; CHECK-4BYTE-NEXT: {{ $}}
335335
; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
336-
; CHECK-4BYTE-NEXT: early-clobber %1:gpr, %2:gpr = PseudoLD_RV32_OPT [[COPY]], 0 :: (load (s32), align 8), (load (s32))
337-
; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD %1, %2
336+
; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 0 :: (load (s32), align 8), (load (s32))
337+
; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT1]]
338338
; CHECK-4BYTE-NEXT: PseudoRET
339339
%0:gpr = COPY $x10
340340
%1:gpr = LW %0, 0 :: (load (s32), align 8)
@@ -626,10 +626,10 @@ body: |
626626
; CHECK-4BYTE-NEXT: {{ $}}
627627
; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
628628
; CHECK-4BYTE-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
629-
; CHECK-4BYTE-NEXT: early-clobber %2:gpr, %3:gpr = PseudoLD_RV32_OPT [[COPY]], 0 :: (load (s32))
630-
; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD %2, %3
631-
; CHECK-4BYTE-NEXT: early-clobber %5:gpr, %6:gpr = PseudoLD_RV32_OPT [[COPY1]], 8 :: (load (s32))
632-
; CHECK-4BYTE-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD %5, %6
629+
; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 0 :: (load (s32))
630+
; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT1]]
631+
; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT2:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT3:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY1]], 8 :: (load (s32))
632+
; CHECK-4BYTE-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT2]], [[PseudoLD_RV32_OPT3]]
633633
; CHECK-4BYTE-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD [[ADD]], [[ADD1]]
634634
; CHECK-4BYTE-NEXT: PseudoRET
635635
%0:gpr = COPY $x10
@@ -695,20 +695,20 @@ body: |
695695
; CHECK-4BYTE: liveins: $x10
696696
; CHECK-4BYTE-NEXT: {{ $}}
697697
; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
698-
; CHECK-4BYTE-NEXT: early-clobber %1:gpr, %2:gpr = PseudoLD_RV32_OPT [[COPY]], 16 :: (load (s32))
699-
; CHECK-4BYTE-NEXT: early-clobber %3:gpr, %4:gpr = PseudoLD_RV32_OPT [[COPY]], 24 :: (load (s32))
700-
; CHECK-4BYTE-NEXT: early-clobber %5:gpr, %6:gpr = PseudoLD_RV32_OPT [[COPY]], 32 :: (load (s32))
701-
; CHECK-4BYTE-NEXT: early-clobber %7:gpr, %8:gpr = PseudoLD_RV32_OPT [[COPY]], 40 :: (load (s32))
702-
; CHECK-4BYTE-NEXT: early-clobber %9:gpr, %10:gpr = PseudoLD_RV32_OPT [[COPY]], 48 :: (load (s32))
703-
; CHECK-4BYTE-NEXT: early-clobber %11:gpr, %12:gpr = PseudoLD_RV32_OPT [[COPY]], 56 :: (load (s32))
704-
; CHECK-4BYTE-NEXT: early-clobber %13:gpr, %14:gpr = PseudoLD_RV32_OPT [[COPY]], 0 :: (load (s32))
705-
; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD %1, %2
706-
; CHECK-4BYTE-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD %3, %4
707-
; CHECK-4BYTE-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD %5, %6
708-
; CHECK-4BYTE-NEXT: [[ADD3:%[0-9]+]]:gpr = ADD %7, %8
709-
; CHECK-4BYTE-NEXT: [[ADD4:%[0-9]+]]:gpr = ADD %9, %10
710-
; CHECK-4BYTE-NEXT: [[ADD5:%[0-9]+]]:gpr = ADD %11, %12
711-
; CHECK-4BYTE-NEXT: [[ADD6:%[0-9]+]]:gpr = ADD %13, %14
698+
; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 16 :: (load (s32))
699+
; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT2:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT3:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 24 :: (load (s32))
700+
; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT4:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT5:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 32 :: (load (s32))
701+
; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT6:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT7:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 40 :: (load (s32))
702+
; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT8:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT9:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 48 :: (load (s32))
703+
; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT10:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT11:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 56 :: (load (s32))
704+
; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT12:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT13:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 0 :: (load (s32))
705+
; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT1]]
706+
; CHECK-4BYTE-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT2]], [[PseudoLD_RV32_OPT3]]
707+
; CHECK-4BYTE-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT4]], [[PseudoLD_RV32_OPT5]]
708+
; CHECK-4BYTE-NEXT: [[ADD3:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT6]], [[PseudoLD_RV32_OPT7]]
709+
; CHECK-4BYTE-NEXT: [[ADD4:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT8]], [[PseudoLD_RV32_OPT9]]
710+
; CHECK-4BYTE-NEXT: [[ADD5:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT10]], [[PseudoLD_RV32_OPT11]]
711+
; CHECK-4BYTE-NEXT: [[ADD6:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT12]], [[PseudoLD_RV32_OPT13]]
712712
; CHECK-4BYTE-NEXT: [[ADD7:%[0-9]+]]:gpr = ADD [[ADD]], [[ADD1]]
713713
; CHECK-4BYTE-NEXT: [[ADD8:%[0-9]+]]:gpr = ADD [[ADD2]], [[ADD3]]
714714
; CHECK-4BYTE-NEXT: [[ADD9:%[0-9]+]]:gpr = ADD [[ADD4]], [[ADD5]]
@@ -777,8 +777,8 @@ body: |
777777
; CHECK-4BYTE: liveins: $x10
778778
; CHECK-4BYTE-NEXT: {{ $}}
779779
; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
780-
; CHECK-4BYTE-NEXT: early-clobber %2:gpr, %1:gpr = PseudoLD_RV32_OPT [[COPY]], 0 :: (load (s32))
781-
; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD %1, %2
780+
; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 0 :: (load (s32))
781+
; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT1]], [[PseudoLD_RV32_OPT]]
782782
; CHECK-4BYTE-NEXT: PseudoRET
783783
%0:gpr = COPY $x10
784784
; Load at higher offset first, then lower offset
@@ -813,8 +813,8 @@ body: |
813813
; CHECK-4BYTE: liveins: $x10
814814
; CHECK-4BYTE-NEXT: {{ $}}
815815
; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
816-
; CHECK-4BYTE-NEXT: early-clobber %1:gpr, %2:gpr = PseudoLD_RV32_OPT [[COPY]], 100 :: (load (s32))
817-
; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD %1, %2
816+
; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 100 :: (load (s32))
817+
; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT1]]
818818
; CHECK-4BYTE-NEXT: PseudoRET
819819
%0:gpr = COPY $x10
820820
; Test with different immediate values that are consecutive
@@ -848,8 +848,8 @@ body: |
848848
; CHECK-4BYTE: liveins: $x10
849849
; CHECK-4BYTE-NEXT: {{ $}}
850850
; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
851-
; CHECK-4BYTE-NEXT: early-clobber %1:gpr, %2:gpr = PseudoLD_RV32_OPT [[COPY]], 2040 :: (load (s32))
852-
; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD %1, %2
851+
; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 2040 :: (load (s32))
852+
; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT1]]
853853
; CHECK-4BYTE-NEXT: PseudoRET
854854
%0:gpr = COPY $x10
855855
; Test with large offset values
@@ -883,8 +883,8 @@ body: |
883883
; CHECK-4BYTE: liveins: $x10
884884
; CHECK-4BYTE-NEXT: {{ $}}
885885
; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
886-
; CHECK-4BYTE-NEXT: early-clobber %1:gpr, %2:gpr = PseudoLD_RV32_OPT [[COPY]], -8 :: (load (s32))
887-
; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD %1, %2
886+
; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], -8 :: (load (s32))
887+
; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT1]]
888888
; CHECK-4BYTE-NEXT: PseudoRET
889889
%0:gpr = COPY $x10
890890
; Test with negative consecutive offsets
@@ -1001,9 +1001,9 @@ body: |
10011001
; CHECK-4BYTE: liveins: $x10
10021002
; CHECK-4BYTE-NEXT: {{ $}}
10031003
; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
1004-
; CHECK-4BYTE-NEXT: early-clobber %1:gpr, %2:gpr = PseudoLD_RV32_OPT [[COPY]], 0 :: (load (s32))
1004+
; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 0 :: (load (s32))
10051005
; CHECK-4BYTE-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 8 :: (load (s32))
1006-
; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD %1, %2
1006+
; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT1]]
10071007
; CHECK-4BYTE-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[ADD]], [[LW]]
10081008
; CHECK-4BYTE-NEXT: PseudoRET
10091009
%0:gpr = COPY $x10
@@ -1107,8 +1107,8 @@ body: |
11071107
; CHECK-4BYTE: liveins: $x10
11081108
; CHECK-4BYTE-NEXT: {{ $}}
11091109
; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
1110-
; CHECK-4BYTE-NEXT: early-clobber %1:gpr, %2:gpr = PseudoLD_RV32_OPT [[COPY]], target-flags(riscv-lo) @global_var :: (load (s32))
1111-
; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD %1, %2
1110+
; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], target-flags(riscv-lo) @global_var :: (load (s32))
1111+
; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT1]]
11121112
; CHECK-4BYTE-NEXT: PseudoRET
11131113
%0:gpr = COPY $x10
11141114
; Two consecutive loads with symbolic global address operands
@@ -1184,8 +1184,8 @@ body: |
11841184
; CHECK-4BYTE: liveins: $x10
11851185
; CHECK-4BYTE-NEXT: {{ $}}
11861186
; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
1187-
; CHECK-4BYTE-NEXT: early-clobber %1:gpr, %2:gpr = PseudoLD_RV32_OPT [[COPY]], target-flags(riscv-lo) %const.0 :: (load (s32))
1188-
; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD %1, %2
1187+
; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], target-flags(riscv-lo) %const.0 :: (load (s32))
1188+
; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT1]]
11891189
; CHECK-4BYTE-NEXT: PseudoRET
11901190
%0:gpr = COPY $x10
11911191
; Two consecutive loads with constant pool operands
@@ -1224,10 +1224,10 @@ body: |
12241224
; CHECK-4BYTE-NEXT: {{ $}}
12251225
; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
12261226
; CHECK-4BYTE-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
1227-
; CHECK-4BYTE-NEXT: early-clobber %2:gpr, %5:gpr = PseudoLD_RV32_OPT [[COPY]], target-flags(riscv-lo) @global_var :: (load (s32))
1228-
; CHECK-4BYTE-NEXT: early-clobber %4:gpr, %3:gpr = PseudoLD_RV32_OPT [[COPY]], 0 :: (load (s32))
1229-
; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD %2, %4
1230-
; CHECK-4BYTE-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD %3, %5
1227+
; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], target-flags(riscv-lo) @global_var :: (load (s32))
1228+
; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT2:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT3:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 0 :: (load (s32))
1229+
; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT2]]
1230+
; CHECK-4BYTE-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT3]], [[PseudoLD_RV32_OPT1]]
12311231
; CHECK-4BYTE-NEXT: PseudoRET
12321232
%0:gpr = COPY $x10
12331233
%1:gpr = COPY $x11

‎llvm/test/CodeGen/RISCV/zilsd-regalloc-hints.mir‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -38,8 +38,8 @@ body: |
3838
; WITH-HINT-LABEL: name: test_load_pair_hints
3939
; WITH-HINT: liveins: $x10
4040
; WITH-HINT-NEXT: {{ $}}
41-
; WITH-HINT-NEXT: early-clobber renamable $x12, renamable $x13 = PseudoLD_RV32_OPT killed renamable $x10, 0 :: (load (s32) from %ir.p), (load (s32) from %ir.p2)
42-
; WITH-HINT-NEXT: renamable $x10 = ADD killed renamable $x12, killed renamable $x13
41+
; WITH-HINT-NEXT: renamable $x10, renamable $x11 = PseudoLD_RV32_OPT killed renamable $x10, 0 :: (load (s32) from %ir.p), (load (s32) from %ir.p2)
42+
; WITH-HINT-NEXT: renamable $x10 = ADD killed renamable $x10, killed renamable $x11
4343
; WITH-HINT-NEXT: PseudoRET implicit $x10
4444
%10:gpr = COPY $x10
4545
; These two LW instructions at offset 0 and 4 should be combined

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