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8 files changed

+218
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‎llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -739,12 +739,12 @@ class CombinerHelper {
739739
void applyTruncSSatU(MachineInstr &MI, Register &MatchInfo) const;
740740

741741
// Combine trunc(umin(x, C)) -> truncusat_u(x).
742-
bool matchTruncUSatU(MachineInstr &MI, Register &MatchInfo) const;
743-
void applyTruncUSatU(MachineInstr &MI, Register &MatchInfo) const;
742+
bool matchTruncUSatU(MachineInstr &MI, MachineInstr &MinMI) const;
743+
void applyTruncUSatU(MachineInstr &MI, MachineInstr &MinMI) const;
744744

745745
// Combine truncusat_u(fptoui(x)) -> fptoui_sat(x)
746-
bool matchTruncUSatUToFPTOUISat(MachineInstr &MI, Register &MatchInfo) const;
747-
void applyTruncUSatUToFPTOUISat(MachineInstr &MI, Register &MatchInfo) const;
746+
bool matchTruncUSatUToFPTOUISat(MachineInstr &MI, MachineInstr &SrcMI) const;
747+
void applyTruncUSatUToFPTOUISat(MachineInstr &MI, MachineInstr &SrcMI) const;
748748

749749
/// Try to transform \p MI by using all of the above
750750
/// combine functions. Returns true if changed.

‎llvm/include/llvm/Target/GlobalISel/Combine.td‎

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1257,15 +1257,17 @@ def trunc_ssatu : GICombineRule<
12571257

12581258
def trunc_usatu : GICombineRule<
12591259
(defs root:$root, register_matchinfo:$matchinfo),
1260-
(match (G_TRUNC $dst, $src):$root,
1261-
[{ return Helper.matchTruncUSatU(*${root}, ${matchinfo}); }]),
1262-
(apply [{ Helper.applyTruncUSatU(*${root}, ${matchinfo}); }])>;
1260+
(match (G_UMIN $min, $x, $y):$Min,
1261+
(G_TRUNC $dst, $min):$root,
1262+
[{ return Helper.matchTruncUSatU(*${root}, *${Min}); }]),
1263+
(apply [{ Helper.applyTruncUSatU(*${root}, *${Min}); }])>;
12631264

12641265
def truncusatu_to_fptouisat : GICombineRule<
12651266
(defs root:$root, register_matchinfo:$matchinfo),
1266-
(match (G_TRUNC_USAT_U $dst, $src):$root,
1267-
[{ return Helper.matchTruncUSatUToFPTOUISat(*${root}, ${matchinfo}); }]),
1268-
(apply [{ Helper.applyTruncUSatUToFPTOUISat(*${root}, ${matchinfo}); }])>;
1267+
(match (G_FPTOUI $src, $x):$Src,
1268+
(G_TRUNC_USAT_U $dst, $src):$root,
1269+
[{ return Helper.matchTruncUSatUToFPTOUISat(*${root}, *${Src}); }]),
1270+
(apply [{ Helper.applyTruncUSatUToFPTOUISat(*${root}, *${Src}); }])>;
12691271

12701272
def truncsat_combines : GICombineGroup<[trunc_ssats, trunc_ssatu, trunc_usatu, truncusatu_to_fptouisat]>;
12711273

‎llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp‎

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -5936,7 +5936,7 @@ bool CombinerHelper::matchTruncSSatS(MachineInstr &MI,
59365936

59375937
APInt SignedMax = APInt::getSignedMaxValue(NumDstBits).sext(NumSrcBits);
59385938
APInt SignedMin = APInt::getSignedMinValue(NumDstBits).sext(NumSrcBits);
5939-
if (isLegal({TargetOpcode::G_TRUNC_SSAT_S, {DstTy, SrcTy}})) {
5939+
if (LI && isLegal({TargetOpcode::G_TRUNC_SSAT_S, {DstTy, SrcTy}})) {
59405940
if (mi_match(
59415941
Src, MRI,
59425942
m_GSMin(m_GSMax(m_Reg(MatchInfo), m_SpecificICstOrSplat(SignedMin)),
@@ -5969,7 +5969,7 @@ bool CombinerHelper::matchTruncSSatU(MachineInstr &MI,
59695969
assert(NumSrcBits > NumDstBits && "Unexpected types for truncate operation");
59705970

59715971
APInt UnsignedMax = APInt::getMaxValue(NumDstBits).zext(NumSrcBits);
5972-
if (isLegal({TargetOpcode::G_TRUNC_SSAT_U, {DstTy, SrcTy}})) {
5972+
if (LI && isLegal({TargetOpcode::G_TRUNC_SSAT_U, {DstTy, SrcTy}})) {
59735973
if (mi_match(Src, MRI,
59745974
m_GSMin(m_GSMax(m_Reg(MatchInfo), m_SpecificICstOrSplat(0)),
59755975
m_SpecificICstOrSplat(UnsignedMax))))
@@ -5995,49 +5995,49 @@ void CombinerHelper::applyTruncSSatU(MachineInstr &MI,
59955995
}
59965996

59975997
bool CombinerHelper::matchTruncUSatU(MachineInstr &MI,
5998-
Register &MatchInfo) const {
5999-
Register Dst = MI.getOperand(0).getReg();
6000-
Register Src = MI.getOperand(1).getReg();
6001-
LLT DstTy = MRI.getType(Dst);
6002-
LLT SrcTy = MRI.getType(Src);
5998+
MachineInstr &MinMI) const {
5999+
Register Min = MinMI.getOperand(2).getReg();
6000+
Register Val = MinMI.getOperand(1).getReg();
6001+
LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
6002+
LLT SrcTy = MRI.getType(Val);
60036003
unsigned NumDstBits = DstTy.getScalarSizeInBits();
60046004
unsigned NumSrcBits = SrcTy.getScalarSizeInBits();
60056005
assert(NumSrcBits > NumDstBits && "Unexpected types for truncate operation");
60066006

60076007
APInt UnsignedMax = APInt::getMaxValue(NumDstBits).zext(NumSrcBits);
6008-
if (isLegal({TargetOpcode::G_TRUNC_SSAT_U, {DstTy, SrcTy}})) {
6009-
if (mi_match(Src, MRI,
6010-
m_GUMin(m_Reg(MatchInfo), m_SpecificICstOrSplat(UnsignedMax))))
6008+
if (LI && isLegal({TargetOpcode::G_TRUNC_SSAT_U, {DstTy, SrcTy}})) {
6009+
if (mi_match(Min, MRI, m_SpecificICstOrSplat(UnsignedMax)) &&
6010+
!mi_match(Val, MRI, m_GSMax(m_Reg(), m_Reg())))
60116011
return true;
60126012
}
60136013
return false;
60146014
}
60156015

60166016
void CombinerHelper::applyTruncUSatU(MachineInstr &MI,
6017-
Register &MatchInfo) const {
6017+
MachineInstr &MinMI) const {
60186018
Register Dst = MI.getOperand(0).getReg();
6019-
Builder.buildTruncUSatU(Dst, MatchInfo);
6019+
Register Src = MinMI.getOperand(1).getReg();
6020+
Builder.buildTruncUSatU(Dst, Src);
60206021
MI.eraseFromParent();
60216022
}
60226023

60236024
bool CombinerHelper::matchTruncUSatUToFPTOUISat(MachineInstr &MI,
6024-
Register &MatchInfo) const {
6025-
Register Dst = MI.getOperand(0).getReg();
6026-
Register Src = MI.getOperand(1).getReg();
6027-
LLT DstTy = MRI.getType(Dst);
6028-
LLT SrcTy = MRI.getType(Src);
6025+
MachineInstr &SrcMI) const {
6026+
LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
6027+
LLT SrcTy = MRI.getType(SrcMI.getOperand(1).getReg());
60296028

6030-
if (isLegalOrBeforeLegalizer({TargetOpcode::G_FPTOUI_SAT, {DstTy, SrcTy}})) {
6031-
if (mi_match(Src, MRI, m_GFPToUI((m_Reg(MatchInfo)))))
6032-
return true;
6029+
if (LI &&
6030+
isLegalOrBeforeLegalizer({TargetOpcode::G_FPTOUI_SAT, {DstTy, SrcTy}})) {
6031+
return true;
60336032
}
60346033
return false;
60356034
}
60366035

60376036
void CombinerHelper::applyTruncUSatUToFPTOUISat(MachineInstr &MI,
6038-
Register &MatchInfo) const {
6037+
MachineInstr &SrcMI) const {
60396038
Register Dst = MI.getOperand(0).getReg();
6040-
Builder.buildFPTOUI_SAT(Dst, MatchInfo);
6039+
Register Src = SrcMI.getOperand(1).getReg();
6040+
Builder.buildFPTOUI_SAT(Dst, Src);
60416041
MI.eraseFromParent();
60426042
}
60436043

‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1647,6 +1647,11 @@ bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
16471647
MachineIRBuilder &MIB = Helper.MIRBuilder;
16481648
MachineRegisterInfo &MRI = *MIB.getMRI();
16491649

1650+
auto LowerUnaryOp = [&MI, &MIB](unsigned Opcode) {
1651+
MIB.buildInstr(Opcode, {MI.getOperand(0)}, {MI.getOperand(2)});
1652+
MI.eraseFromParent();
1653+
return true;
1654+
};
16501655
auto LowerUnaryOp = [&MI, &MIB](unsigned Opcode) {
16511656
MIB.buildInstr(Opcode, {MI.getOperand(0)}, {MI.getOperand(2)});
16521657
MI.eraseFromParent();

‎llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll‎

Lines changed: 54 additions & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -716,15 +716,15 @@ entry:
716716
}
717717

718718
define <8 x i16> @stest_f16i16(<8 x half> %x) {
719-
; CHECK-CVT-SD-LABEL: stest_f16i16:
720-
; CHECK-CVT-SD: // %bb.0: // %entry
721-
; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v0.4h
722-
; CHECK-CVT-SD-NEXT: fcvtl2 v0.4s, v0.8h
723-
; CHECK-CVT-SD-NEXT: fcvtzs v1.4s, v1.4s
724-
; CHECK-CVT-SD-NEXT: fcvtzs v2.4s, v0.4s
725-
; CHECK-CVT-SD-NEXT: sqxtn v0.4h, v1.4s
726-
; CHECK-CVT-SD-NEXT: sqxtn2 v0.8h, v2.4s
727-
; CHECK-CVT-SD-NEXT: ret
719+
; CHECK-CVT-LABEL: stest_f16i16:
720+
; CHECK-CVT: // %bb.0: // %entry
721+
; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
722+
; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
723+
; CHECK-CVT-NEXT: fcvtzs v1.4s, v1.4s
724+
; CHECK-CVT-NEXT: fcvtzs v2.4s, v0.4s
725+
; CHECK-CVT-NEXT: sqxtn v0.4h, v1.4s
726+
; CHECK-CVT-NEXT: sqxtn2 v0.8h, v2.4s
727+
; CHECK-CVT-NEXT: ret
728728
;
729729
; CHECK-FP16-SD-LABEL: stest_f16i16:
730730
; CHECK-FP16-SD: // %bb.0: // %entry
@@ -771,15 +771,15 @@ entry:
771771
}
772772

773773
define <8 x i16> @utesth_f16i16(<8 x half> %x) {
774-
; CHECK-CVT-SD-LABEL: utesth_f16i16:
775-
; CHECK-CVT-SD: // %bb.0: // %entry
776-
; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v0.4h
777-
; CHECK-CVT-SD-NEXT: fcvtl2 v0.4s, v0.8h
778-
; CHECK-CVT-SD-NEXT: fcvtzu v1.4s, v1.4s
779-
; CHECK-CVT-SD-NEXT: fcvtzu v2.4s, v0.4s
780-
; CHECK-CVT-SD-NEXT: uqxtn v0.4h, v1.4s
781-
; CHECK-CVT-SD-NEXT: uqxtn2 v0.8h, v2.4s
782-
; CHECK-CVT-SD-NEXT: ret
774+
; CHECK-CVT-LABEL: utesth_f16i16:
775+
; CHECK-CVT: // %bb.0: // %entry
776+
; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
777+
; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
778+
; CHECK-CVT-NEXT: fcvtzu v1.4s, v1.4s
779+
; CHECK-CVT-NEXT: fcvtzu v2.4s, v0.4s
780+
; CHECK-CVT-NEXT: uqxtn v0.4h, v1.4s
781+
; CHECK-CVT-NEXT: uqxtn2 v0.8h, v2.4s
782+
; CHECK-CVT-NEXT: ret
783783
;
784784
; CHECK-FP16-SD-LABEL: utesth_f16i16:
785785
; CHECK-FP16-SD: // %bb.0: // %entry
@@ -818,15 +818,15 @@ entry:
818818
}
819819

820820
define <8 x i16> @ustest_f16i16(<8 x half> %x) {
821-
; CHECK-CVT-SD-LABEL: ustest_f16i16:
822-
; CHECK-CVT-SD: // %bb.0: // %entry
823-
; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v0.4h
824-
; CHECK-CVT-SD-NEXT: fcvtl2 v0.4s, v0.8h
825-
; CHECK-CVT-SD-NEXT: fcvtzs v1.4s, v1.4s
826-
; CHECK-CVT-SD-NEXT: fcvtzs v2.4s, v0.4s
827-
; CHECK-CVT-SD-NEXT: sqxtun v0.4h, v1.4s
828-
; CHECK-CVT-SD-NEXT: sqxtun2 v0.8h, v2.4s
829-
; CHECK-CVT-SD-NEXT: ret
821+
; CHECK-CVT-LABEL: ustest_f16i16:
822+
; CHECK-CVT: // %bb.0: // %entry
823+
; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
824+
; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
825+
; CHECK-CVT-NEXT: fcvtzs v1.4s, v1.4s
826+
; CHECK-CVT-NEXT: fcvtzs v2.4s, v0.4s
827+
; CHECK-CVT-NEXT: sqxtun v0.4h, v1.4s
828+
; CHECK-CVT-NEXT: sqxtun2 v0.8h, v2.4s
829+
; CHECK-CVT-NEXT: ret
830830
;
831831
; CHECK-FP16-SD-LABEL: ustest_f16i16:
832832
; CHECK-FP16-SD: // %bb.0: // %entry
@@ -2879,15 +2879,15 @@ entry:
28792879
}
28802880

28812881
define <8 x i16> @stest_f16i16_mm(<8 x half> %x) {
2882-
; CHECK-CVT-SD-LABEL: stest_f16i16_mm:
2883-
; CHECK-CVT-SD: // %bb.0: // %entry
2884-
; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v0.4h
2885-
; CHECK-CVT-SD-NEXT: fcvtl2 v0.4s, v0.8h
2886-
; CHECK-CVT-SD-NEXT: fcvtzs v1.4s, v1.4s
2887-
; CHECK-CVT-SD-NEXT: fcvtzs v2.4s, v0.4s
2888-
; CHECK-CVT-SD-NEXT: sqxtn v0.4h, v1.4s
2889-
; CHECK-CVT-SD-NEXT: sqxtn2 v0.8h, v2.4s
2890-
; CHECK-CVT-SD-NEXT: ret
2882+
; CHECK-CVT-LABEL: stest_f16i16_mm:
2883+
; CHECK-CVT: // %bb.0: // %entry
2884+
; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
2885+
; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
2886+
; CHECK-CVT-NEXT: fcvtzs v1.4s, v1.4s
2887+
; CHECK-CVT-NEXT: fcvtzs v2.4s, v0.4s
2888+
; CHECK-CVT-NEXT: sqxtn v0.4h, v1.4s
2889+
; CHECK-CVT-NEXT: sqxtn2 v0.8h, v2.4s
2890+
; CHECK-CVT-NEXT: ret
28912891
;
28922892
; CHECK-FP16-SD-LABEL: stest_f16i16_mm:
28932893
; CHECK-FP16-SD: // %bb.0: // %entry
@@ -2932,15 +2932,15 @@ entry:
29322932
}
29332933

29342934
define <8 x i16> @utesth_f16i16_mm(<8 x half> %x) {
2935-
; CHECK-CVT-SD-LABEL: utesth_f16i16_mm:
2936-
; CHECK-CVT-SD: // %bb.0: // %entry
2937-
; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v0.4h
2938-
; CHECK-CVT-SD-NEXT: fcvtl2 v0.4s, v0.8h
2939-
; CHECK-CVT-SD-NEXT: fcvtzu v1.4s, v1.4s
2940-
; CHECK-CVT-SD-NEXT: fcvtzu v2.4s, v0.4s
2941-
; CHECK-CVT-SD-NEXT: uqxtn v0.4h, v1.4s
2942-
; CHECK-CVT-SD-NEXT: uqxtn2 v0.8h, v2.4s
2943-
; CHECK-CVT-SD-NEXT: ret
2935+
; CHECK-CVT-LABEL: utesth_f16i16_mm:
2936+
; CHECK-CVT: // %bb.0: // %entry
2937+
; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
2938+
; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
2939+
; CHECK-CVT-NEXT: fcvtzu v1.4s, v1.4s
2940+
; CHECK-CVT-NEXT: fcvtzu v2.4s, v0.4s
2941+
; CHECK-CVT-NEXT: uqxtn v0.4h, v1.4s
2942+
; CHECK-CVT-NEXT: uqxtn2 v0.8h, v2.4s
2943+
; CHECK-CVT-NEXT: ret
29442944
;
29452945
; CHECK-FP16-SD-LABEL: utesth_f16i16_mm:
29462946
; CHECK-FP16-SD: // %bb.0: // %entry
@@ -2978,15 +2978,15 @@ entry:
29782978
}
29792979

29802980
define <8 x i16> @ustest_f16i16_mm(<8 x half> %x) {
2981-
; CHECK-CVT-SD-LABEL: ustest_f16i16_mm:
2982-
; CHECK-CVT-SD: // %bb.0: // %entry
2983-
; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v0.4h
2984-
; CHECK-CVT-SD-NEXT: fcvtl2 v0.4s, v0.8h
2985-
; CHECK-CVT-SD-NEXT: fcvtzs v1.4s, v1.4s
2986-
; CHECK-CVT-SD-NEXT: fcvtzs v2.4s, v0.4s
2987-
; CHECK-CVT-SD-NEXT: sqxtun v0.4h, v1.4s
2988-
; CHECK-CVT-SD-NEXT: sqxtun2 v0.8h, v2.4s
2989-
; CHECK-CVT-SD-NEXT: ret
2981+
; CHECK-CVT-LABEL: ustest_f16i16_mm:
2982+
; CHECK-CVT: // %bb.0: // %entry
2983+
; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
2984+
; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
2985+
; CHECK-CVT-NEXT: fcvtzs v1.4s, v1.4s
2986+
; CHECK-CVT-NEXT: fcvtzs v2.4s, v0.4s
2987+
; CHECK-CVT-NEXT: sqxtun v0.4h, v1.4s
2988+
; CHECK-CVT-NEXT: sqxtun2 v0.8h, v2.4s
2989+
; CHECK-CVT-NEXT: ret
29902990
;
29912991
; CHECK-FP16-SD-LABEL: ustest_f16i16_mm:
29922992
; CHECK-FP16-SD: // %bb.0: // %entry

‎llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll‎

Lines changed: 18 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -2939,12 +2939,12 @@ define <4 x i13> @test_signed_v4f16_v4i13(<4 x half> %f) {
29392939
}
29402940

29412941
define <4 x i16> @test_signed_v4f16_v4i16(<4 x half> %f) {
2942-
; CHECK-SD-CVT-LABEL: test_signed_v4f16_v4i16:
2943-
; CHECK-SD-CVT: // %bb.0:
2944-
; CHECK-SD-CVT-NEXT: fcvtl v0.4s, v0.4h
2945-
; CHECK-SD-CVT-NEXT: fcvtzs v0.4s, v0.4s
2946-
; CHECK-SD-CVT-NEXT: sqxtn v0.4h, v0.4s
2947-
; CHECK-SD-CVT-NEXT: ret
2942+
; CHECK-CVT-LABEL: test_signed_v4f16_v4i16:
2943+
; CHECK-CVT: // %bb.0:
2944+
; CHECK-CVT-NEXT: fcvtl v0.4s, v0.4h
2945+
; CHECK-CVT-NEXT: fcvtzs v0.4s, v0.4s
2946+
; CHECK-CVT-NEXT: sqxtn v0.4h, v0.4s
2947+
; CHECK-CVT-NEXT: ret
29482948
;
29492949
; CHECK-FP16-LABEL: test_signed_v4f16_v4i16:
29502950
; CHECK-FP16: // %bb.0:
@@ -3475,11 +3475,11 @@ define <8 x i8> @test_signed_v8f16_v8i8(<8 x half> %f) {
34753475
; CHECK-SD-CVT-NEXT: xtn v0.8b, v0.8h
34763476
; CHECK-SD-CVT-NEXT: ret
34773477
;
3478-
; CHECK-SD-FP16-LABEL: test_signed_v8f16_v8i8:
3479-
; CHECK-SD-FP16: // %bb.0:
3480-
; CHECK-SD-FP16-NEXT: fcvtzs v0.8h, v0.8h
3481-
; CHECK-SD-FP16-NEXT: sqxtn v0.8b, v0.8h
3482-
; CHECK-SD-FP16-NEXT: ret
3478+
; CHECK-FP16-LABEL: test_signed_v8f16_v8i8:
3479+
; CHECK-FP16: // %bb.0:
3480+
; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h
3481+
; CHECK-FP16-NEXT: sqxtn v0.8b, v0.8h
3482+
; CHECK-FP16-NEXT: ret
34833483
;
34843484
; CHECK-GI-CVT-LABEL: test_signed_v8f16_v8i8:
34853485
; CHECK-GI-CVT: // %bb.0:
@@ -3496,12 +3496,6 @@ define <8 x i8> @test_signed_v8f16_v8i8(<8 x half> %f) {
34963496
; CHECK-GI-CVT-NEXT: uzp1 v0.8h, v2.8h, v0.8h
34973497
; CHECK-GI-CVT-NEXT: xtn v0.8b, v0.8h
34983498
; CHECK-GI-CVT-NEXT: ret
3499-
;
3500-
; CHECK-GI-FP16-LABEL: test_signed_v8f16_v8i8:
3501-
; CHECK-GI-FP16: // %bb.0:
3502-
; CHECK-GI-FP16-NEXT: fcvtzs v0.8h, v0.8h
3503-
; CHECK-GI-FP16-NEXT: sqxtn v0.8b, v0.8h
3504-
; CHECK-GI-FP16-NEXT: ret
35053499
%x = call <8 x i8> @llvm.fptosi.sat.v8f16.v8i8(<8 x half> %f)
35063500
ret <8 x i8> %x
35073501
}
@@ -4474,13 +4468,13 @@ define <16 x i8> @test_signed_v16f16_v16i8(<16 x half> %f) {
44744468
; CHECK-SD-CVT-NEXT: uzp1 v0.16b, v0.16b, v1.16b
44754469
; CHECK-SD-CVT-NEXT: ret
44764470
;
4477-
; CHECK-SD-FP16-LABEL: test_signed_v16f16_v16i8:
4478-
; CHECK-SD-FP16: // %bb.0:
4479-
; CHECK-SD-FP16-NEXT: fcvtzs v0.8h, v0.8h
4480-
; CHECK-SD-FP16-NEXT: fcvtzs v1.8h, v1.8h
4481-
; CHECK-SD-FP16-NEXT: sqxtn v0.8b, v0.8h
4482-
; CHECK-SD-FP16-NEXT: sqxtn2 v0.16b, v1.8h
4483-
; CHECK-SD-FP16-NEXT: ret
4471+
; CHECK-FP16-LABEL: test_signed_v16f16_v16i8:
4472+
; CHECK-FP16: // %bb.0:
4473+
; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h
4474+
; CHECK-FP16-NEXT: fcvtzs v1.8h, v1.8h
4475+
; CHECK-FP16-NEXT: sqxtn v0.8b, v0.8h
4476+
; CHECK-FP16-NEXT: sqxtn2 v0.16b, v1.8h
4477+
; CHECK-FP16-NEXT: ret
44844478
;
44854479
; CHECK-GI-CVT-LABEL: test_signed_v16f16_v16i8:
44864480
; CHECK-GI-CVT: // %bb.0:
@@ -4506,14 +4500,6 @@ define <16 x i8> @test_signed_v16f16_v16i8(<16 x half> %f) {
45064500
; CHECK-GI-CVT-NEXT: uzp1 v1.8h, v3.8h, v1.8h
45074501
; CHECK-GI-CVT-NEXT: uzp1 v0.16b, v0.16b, v1.16b
45084502
; CHECK-GI-CVT-NEXT: ret
4509-
;
4510-
; CHECK-GI-FP16-LABEL: test_signed_v16f16_v16i8:
4511-
; CHECK-GI-FP16: // %bb.0:
4512-
; CHECK-GI-FP16-NEXT: fcvtzs v0.8h, v0.8h
4513-
; CHECK-GI-FP16-NEXT: fcvtzs v1.8h, v1.8h
4514-
; CHECK-GI-FP16-NEXT: sqxtn v0.8b, v0.8h
4515-
; CHECK-GI-FP16-NEXT: sqxtn2 v0.16b, v1.8h
4516-
; CHECK-GI-FP16-NEXT: ret
45174503
%x = call <16 x i8> @llvm.fptosi.sat.v16f16.v16i8(<16 x half> %f)
45184504
ret <16 x i8> %x
45194505
}

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