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Zaara Syeda
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Address review comments
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-80
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4 files changed

+61
-80
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‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp‎

Lines changed: 4 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -11986,21 +11986,15 @@ SDValue PPCTargetLowering::LowerUaddo(SDValue Op, SelectionDAG &DAG) const {
1198611986
return SDValue();
1198711987

1198811988
EVT VT = Op.getNode()->getValueType(0);
11989-
bool is64Bit = Subtarget.isPPC64();
1199011989

1199111990
SDValue ADDC;
1199211991
SDValue Overflow;
1199311992
SDVTList VTs = Op.getNode()->getVTList();
1199411993

11995-
ADDC = SDValue(DAG.getMachineNode(is64Bit ? PPC::ADDC8 : PPC::ADDC, dl, VT,
11996-
MVT::Glue, LHS, RHS),
11997-
0);
11998-
SDValue Li = SDValue(DAG.getMachineNode(is64Bit ? PPC::LI8 : PPC::LI, dl, VT,
11999-
DAG.getTargetConstant(0, dl, VT)),
12000-
0);
12001-
Overflow = SDValue(DAG.getMachineNode(is64Bit ? PPC::ADDZE8 : PPC::ADDZE, dl,
12002-
VT, MVT::Glue, Li, ADDC.getValue(1)),
12003-
0);
11994+
ADDC = DAG.getNode(ISD::ADDC, dl, DAG.getVTList(VT, MVT::Glue), LHS, RHS);
11995+
Overflow = DAG.getNode(ISD::ADDE, dl, DAG.getVTList(VT, MVT::Glue),
11996+
DAG.getConstant(0, dl, VT), DAG.getConstant(0, dl, VT),
11997+
ADDC.getValue(1));
1200411998
SDValue OverflowTrunc =
1200511999
DAG.getNode(ISD::TRUNCATE, dl, Op.getNode()->getValueType(1), Overflow);
1200612000
SDValue Res =

‎llvm/lib/Target/PowerPC/PPCMIPeephole.cpp‎

Lines changed: 6 additions & 55 deletions
Original file line numberDiff line numberDiff line change
@@ -139,8 +139,6 @@ struct PPCMIPeephole : public MachineFunctionPass {
139139
void UpdateTOCSaves(std::map<MachineInstr *, bool> &TOCSaves,
140140
MachineInstr *MI);
141141

142-
bool eliminateTruncWhenLoweringUADDO(MachineInstr &MI,
143-
MachineInstr *&ToErase);
144142
// A number of transformations will eliminate the definition of a register
145143
// as all of its uses will be removed. However, this leaves a register
146144
// without a definition for LiveVariables. Such transformations should
@@ -1073,18 +1071,6 @@ bool PPCMIPeephole::simplifyCode() {
10731071
break;
10741072
}
10751073
case PPC::RLDICL: {
1076-
Register SrcReg = MI.getOperand(1).getReg();
1077-
if (!SrcReg.isVirtual())
1078-
break;
1079-
1080-
MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
1081-
// We can eliminate clearing the left 63 bits when only the carry-bit is
1082-
// set.
1083-
if (eliminateTruncWhenLoweringUADDO(MI, ToErase)) {
1084-
Simplified = true;
1085-
break;
1086-
}
1087-
10881074
// We can eliminate RLDICL (e.g. for zero-extension)
10891075
// if all bits to clear are already zero in the input.
10901076
// This code assume following code sequence for zero-extension.
@@ -1096,6 +1082,11 @@ bool PPCMIPeephole::simplifyCode() {
10961082
if (MI.getOperand(2).getImm() != 0)
10971083
break;
10981084

1085+
Register SrcReg = MI.getOperand(1).getReg();
1086+
if (!SrcReg.isVirtual())
1087+
break;
1088+
1089+
MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
10991090
if (!(SrcMI && SrcMI->getOpcode() == PPC::INSERT_SUBREG &&
11001091
SrcMI->getOperand(0).isReg() && SrcMI->getOperand(1).isReg()))
11011092
break;
@@ -1286,15 +1277,7 @@ bool PPCMIPeephole::simplifyCode() {
12861277
Simplified = true;
12871278
break;
12881279
}
1289-
case PPC::RLWINM: {
1290-
// We can eliminate clearing the left 31 bits when only the carry-bit is
1291-
// set.
1292-
if (eliminateTruncWhenLoweringUADDO(MI, ToErase)) {
1293-
Simplified = true;
1294-
break;
1295-
}
1296-
}
1297-
LLVM_FALLTHROUGH;
1280+
case PPC::RLWINM:
12981281
case PPC::RLWINM_rec:
12991282
case PPC::RLWINM8:
13001283
case PPC::RLWINM8_rec: {
@@ -1906,38 +1889,6 @@ bool PPCMIPeephole::eliminateRedundantCompare() {
19061889

19071890
return Simplified;
19081891
}
1909-
bool PPCMIPeephole::eliminateTruncWhenLoweringUADDO(MachineInstr &MI,
1910-
MachineInstr *&ToErase) {
1911-
Register SrcReg = MI.getOperand(1).getReg();
1912-
if (!SrcReg.isVirtual())
1913-
return false;
1914-
MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
1915-
1916-
bool Is64Bit = MI.getOpcode() == PPC::RLDICL;
1917-
int Imm = Is64Bit ? 63 : 31;
1918-
if (MI.getOperand(2).getImm() != 0 || MI.getOperand(3).getImm() != Imm)
1919-
return false;
1920-
if (SrcMI->getOpcode() != (Is64Bit ? PPC::ADDZE8 : PPC::ADDZE))
1921-
return false;
1922-
MachineInstr *LI = MRI->getVRegDef(SrcMI->getOperand(1).getReg());
1923-
if (LI->getOpcode() != (Is64Bit ? PPC::LI8 : PPC::LI))
1924-
return false;
1925-
if (LI->getOperand(1).getImm() != 0 || MI.getOperand(2).getImm() != 0)
1926-
return false;
1927-
Register NewReg = SrcMI->getOperand(0).getReg();
1928-
ToErase = &MI;
1929-
Register MIDestReg = MI.getOperand(0).getReg();
1930-
for (MachineInstr &UseMI : MRI->use_instructions(MIDestReg)) {
1931-
for (MachineOperand &MO : UseMI.operands()) {
1932-
if (MO.isReg() && MO.getReg() == MIDestReg) {
1933-
MO.setReg(NewReg);
1934-
addRegToUpdate(NewReg);
1935-
break;
1936-
}
1937-
}
1938-
}
1939-
return true;
1940-
}
19411892

19421893
// We miss the opportunity to emit an RLDIC when lowering jump tables
19431894
// since ISEL sees only a single basic block. When selecting, the clear

‎llvm/test/CodeGen/PowerPC/uaddo-32.ll‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
22
; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s
3+
; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -mcpu=pwr10 | FileCheck %s --check-prefixes=CHECKP10
34

45
define noundef i32 @add(i32 noundef %a, i32 noundef %b, ptr nocapture noundef writeonly %ovf) {
56
; CHECK-LABEL: add:
@@ -9,6 +10,15 @@ define noundef i32 @add(i32 noundef %a, i32 noundef %b, ptr nocapture noundef wr
910
; CHECK-NEXT: addze 4, 6
1011
; CHECK-NEXT: stw 4, 0(5)
1112
; CHECK-NEXT: blr
13+
14+
; CHECKP10-LABEL: add:
15+
; CHECKP10: # %bb.0: # %entry
16+
; CHECKP10-NEXT: add 4, 3, 4
17+
; CHECKP10-NEXT: cmplw 4, 3
18+
; CHECKP10-NEXT: setbc 3, 0
19+
; CHECKP10-NEXT: stw 3, 0(5)
20+
; CHECKP10-NEXT: mr 3, 4
21+
; CHECKP10-NEXT: blr
1222
entry:
1323
%0 = tail call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
1424
%1 = extractvalue { i32, i1 } %0, 1
@@ -28,6 +38,14 @@ define noundef zeroext i1 @add_overflow(i32 noundef %a, i32 noundef %b, ptr noca
2838
; CHECK-NEXT: addze 3, 6
2939
; CHECK-NEXT: stw 4, 0(5)
3040
; CHECK-NEXT: blr
41+
42+
; CHECKP10-LABEL: add_overflow:
43+
; CHECKP10: # %bb.0: # %entry
44+
; CHECKP10-NEXT: add 4, 3, 4
45+
; CHECKP10-NEXT: cmplw 4, 3
46+
; CHECKP10-NEXT: stw 4, 0(5)
47+
; CHECKP10-NEXT: setbc 3, 0
48+
; CHECKP10-NEXT: blr
3149
entry:
3250
%0 = tail call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
3351
%1 = extractvalue { i32, i1 } %0, 1

‎llvm/test/CodeGen/PowerPC/uaddo-64.ll‎

Lines changed: 33 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1,14 +1,24 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2-
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s --check-prefixes=PPC64
2+
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s
3+
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr10 | FileCheck %s --check-prefixes=CHECKP10
34

45
define noundef i64 @add(i64 noundef %a, i64 noundef %b, ptr nocapture noundef writeonly %ovf) {
5-
; PPC64-LABEL: add:
6-
; PPC64: # %bb.0: # %entry
7-
; PPC64-NEXT: li 6, 0
8-
; PPC64-NEXT: addc 3, 3, 4
9-
; PPC64-NEXT: addze 4, 6
10-
; PPC64-NEXT: std 4, 0(5)
11-
; PPC64-NEXT: blr
6+
; CHECK-LABEL: add:
7+
; CHECK: # %bb.0: # %entry
8+
; CHECK-NEXT: li 6, 0
9+
; CHECK-NEXT: addc 3, 3, 4
10+
; CHECK-NEXT: addze 4, 6
11+
; CHECK-NEXT: std 4, 0(5)
12+
; CHECK-NEXT: blr
13+
14+
; CHECKP10-LABEL: add:
15+
; CHECKP10: # %bb.0: # %entry
16+
; CHECKP10-NEXT: add 4, 3, 4
17+
; CHECKP10-NEXT: cmpld 4, 3
18+
; CHECKP10-NEXT: setbc 3, 0
19+
; CHECKP10-NEXT: std 3, 0(5)
20+
; CHECKP10-NEXT: mr 3, 4
21+
; CHECKP10-NEXT: blr
1222
entry:
1323
%0 = tail call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
1424
%1 = extractvalue { i64, i1 } %0, 1
@@ -21,13 +31,21 @@ entry:
2131
declare { i64, i1 } @llvm.uadd.with.overflow.i64(i64, i64)
2232

2333
define noundef zeroext i1 @add_overflow(i64 noundef %a, i64 noundef %b, ptr nocapture noundef writeonly %ovf) {
24-
; PPC64-LABEL: add_overflow:
25-
; PPC64: # %bb.0: # %entry
26-
; PPC64-NEXT: li 6, 0
27-
; PPC64-NEXT: addc 4, 3, 4
28-
; PPC64-NEXT: addze 3, 6
29-
; PPC64-NEXT: std 4, 0(5)
30-
; PPC64-NEXT: blr
34+
; CHECK-LABEL: add_overflow:
35+
; CHECK: # %bb.0: # %entry
36+
; CHECK-NEXT: li 6, 0
37+
; CHECK-NEXT: addc 4, 3, 4
38+
; CHECK-NEXT: addze 3, 6
39+
; CHECK-NEXT: std 4, 0(5)
40+
; CHECK-NEXT: blr
41+
42+
; CHECKP10-LABEL: add_overflow:
43+
; CHECKP10: # %bb.0: # %entry
44+
; CHECKP10-NEXT: add 4, 3, 4
45+
; CHECKP10-NEXT: cmpld 4, 3
46+
; CHECKP10-NEXT: std 4, 0(5)
47+
; CHECKP10-NEXT: setbc 3, 0
48+
; CHECKP10-NEXT: blr
3149
entry:
3250
%0 = tail call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
3351
%1 = extractvalue { i64, i1 } %0, 1

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