[CodeGen][NFC] Properly split MachineLICM and EarlyMachineLICM

Both are based on MachineLICMBase, and the functionality there is
"switched" based on a PreRegAlloc flag. This commit is simply about
trusting the original value of that flag, instead of overwriting it
based on MRI.isSSA(), which is un-reliable

Author: gbossu

llvm/lib/CodeGen/MachineLICM.cpp

@@ -391,12 +391,6 @@ bool MachineLICMImpl::run(MachineFunction &MF) {
   MRI = &MF.getRegInfo();
   SchedModel.init(&ST);
 
-  // FIXME: Remove this assignment or convert to an assert? (dead variable PreRegAlloc)
-  // MachineLICM and PostRAMachineLICM were distinguished by introducing
-  // EarlyMachineLICM and MachineLICM respectively to avoid "using an unreliable
-  // MRI::isSSA() check to determine whether register allocation has happened"
-  // (See 4a7c8e7).
-  PreRegAlloc = MRI->isSSA();
   HasProfileData = MF.getFunction().hasProfileData();
 
   if (PreRegAlloc)

llvm/test/CodeGen/AArch64/mlicm-stack-write-check.mir

@@ -3,9 +3,6 @@
 ---
 name: test
 tracksRegLiveness: true
-isSSA: false
-registers:
-  - { id: 0, class: gpr64 }
 stack:
   - { id: 0, size: 8, type: spill-slot }
 body: |
@@ -30,14 +27,11 @@ body: |
 
   bb.2:
     liveins: $x0
-    %0 = COPY $x0
 ...
+
 ---
 name: test2
 tracksRegLiveness: true
-isSSA: false
-registers:
-  - { id: 0, class: gpr64 }
 stack:
   - { id: 0, size: 8, type: spill-slot }
 body: |
@@ -62,5 +56,4 @@ body: |
 
   bb.2:
     liveins: $x0
-    %0 = COPY $x0
 ...

llvm/test/CodeGen/AMDGPU/licm-regpressure.mir

@@ -1,6 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass machinelicm -o - %s | FileCheck -check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -passes machinelicm -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass early-machinelicm -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -passes early-machinelicm -o - %s | FileCheck -check-prefix=GCN %s
 
 # MachineLICM shall limit hoisting of V_CVT instructions out of the loop keeping
 # register pressure within the budget. VGPR budget at occupancy 10 is 24 vgprs.

llvm/test/CodeGen/AMDGPU/licm-valu.mir

@@ -1,6 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=machinelicm -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=machinelicm -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=early-machinelicm -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=early-machinelicm -o - %s | FileCheck -check-prefix=GCN %s
 
 ---
 name: hoist_move

llvm/test/CodeGen/X86/unfoldMemoryOperand.mir

@@ -1,6 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=x86_64-- -passes machinelicm -mcpu=skx -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64-- -passes early-machinelicm -mcpu=skx -verify-machineinstrs -o - %s | FileCheck %s
 --- |
   @x = dso_local global i32 0, align 4
   @z = dso_local local_unnamed_addr global [1024 x i32] zeroinitializer, align 16

llvm/test/DebugInfo/MIR/X86/mlicm-hoist-pre-regalloc.mir

@@ -1,6 +1,6 @@
 --- | 
-  ; RUN: llc -run-pass=machinelicm -o - %s | FileCheck %s
-  ; RUN: llc -passes=machinelicm -o - %s | FileCheck %s
+  ; RUN: llc -run-pass=early-machinelicm -o - %s | FileCheck %s
+  ; RUN: llc -passes=early-machinelicm -o - %s | FileCheck %s
   ; Line numbers should not be retained when loop invariant instructions are hoisted.
   ; Doing so causes poor stepping bevavior.
   ;