Fix default value for -mapx-relax-relocations option.

Rename the pass of suppressing APX features for relocation.

Author: fzou1

clang/include/clang/Basic/CodeGenOptions.def

@@ -201,7 +201,7 @@ CODEGENOPT(UniqueInternalLinkageNames, 1, 0) ///< Internal Linkage symbols get u
 CODEGENOPT(SplitMachineFunctions, 1, 0) ///< Split machine functions using profile information.
 CODEGENOPT(PPCUseFullRegisterNames, 1, 0) ///< Print full register names in assembly
 CODEGENOPT(X86RelaxRelocations, 1, 1) ///< -Wa,-mrelax-relocations={yes,no}
-CODEGENOPT(X86APXRelaxRelocations, 1, 0) ///< -Wa,-mrelax-relocations={yes,no}
+CODEGENOPT(X86APXRelaxRelocations, 1, 0) ///< -Wa,-mapx-relax-relocations={yes,no}
 CODEGENOPT(X86Sse2Avx        , 1, 0)   ///< -Wa,-msse2avx
 
 /// When false, this attempts to generate code as if the result of an

clang/include/clang/Driver/Options.td

@@ -7444,7 +7444,7 @@ def mrelax_relocations_no : Flag<["-"], "mrelax-relocations=no">,
     MarshallingInfoNegativeFlag<CodeGenOpts<"X86RelaxRelocations">>;
 def mapx_relax_relocations_yes : Flag<["-"], "mapx-relax-relocations=yes">,
     HelpText<"Enable x86 APX relax relocations">,
-    MarshallingInfoNegativeFlag<CodeGenOpts<"X86APXRelaxRelocations">>;
+    MarshallingInfoFlag<CodeGenOpts<"X86APXRelaxRelocations">>;
 def msave_temp_labels : Flag<["-"], "msave-temp-labels">,
   HelpText<"Save temporary labels in the symbol table. "
            "Note this may change .s semantics and shouldn't generally be used "

llvm/lib/Target/X86/CMakeLists.txt

@@ -89,7 +89,7 @@ set(sources
   GISel/X86InstructionSelector.cpp
   GISel/X86LegalizerInfo.cpp
   GISel/X86RegisterBankInfo.cpp
-  X86SuppressEGPRAndNDDForReloc.cpp
+  X86SuppressAPXForReloc.cpp
   )
 
 add_llvm_target(X86CodeGen ${sources}

llvm/lib/Target/X86/X86.h

@@ -169,7 +169,7 @@ FunctionPass *createX86LoadValueInjectionRetHardeningPass();
 FunctionPass *createX86SpeculativeLoadHardeningPass();
 FunctionPass *createX86SpeculativeExecutionSideEffectSuppression();
 FunctionPass *createX86ArgumentStackSlotPass();
-FunctionPass *createX86SuppressEGPRAndNDDForRelocPass();
+FunctionPass *createX86SuppressAPXForRelocationPass();
 
 void initializeCompressEVEXPassPass(PassRegistry &);
 void initializeFPSPass(PassRegistry &);
@@ -205,6 +205,7 @@ void initializeX86ReturnThunksPass(PassRegistry &);
 void initializeX86SpeculativeExecutionSideEffectSuppressionPass(PassRegistry &);
 void initializeX86SpeculativeLoadHardeningPassPass(PassRegistry &);
 void initializeX86TileConfigPass(PassRegistry &);
+void initializeX86SuppressAPXForRelocationPassPass(PassRegistry &);
 
 namespace X86AS {
 enum : unsigned {

llvm/lib/Target/X86/X86SuppressEGPRAndNDDForReloc.cpp renamed to llvm/lib/Target/X86/X86SuppressAPXForReloc.cpp

@@ -1,4 +1,4 @@
-//==- X86SuppressEGPRAndNDDForReloc.cpp - Suppress EGPR/NDD for relocations -=//
+//===- X86SuppressAPXForReloc.cpp - Suppress APX features for relocations -===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
@@ -7,12 +7,12 @@
 //===----------------------------------------------------------------------===//
 /// \file
 ///
-/// This pass is added to suppress EGPR and NDD for relocations. It's used
+/// This pass is added to suppress APX features for relocations. It's used
 /// together with disabling emitting APX relocation types for backward
 /// compatibility with old version of linker (like before LD 2.43). It can avoid
 /// the instructions updated incorrectly by old version of linker if the
-/// instructions are with APX EGPR/NDD features + the relocations other than APX
-/// ones (like GOTTPOFF).
+/// instructions are with APX EGPR/NDD/NF features + the relocations other than
+/// APX ones (like GOTTPOFF).
 ///
 //===----------------------------------------------------------------------===//
 
@@ -23,44 +23,52 @@
 #include "X86Subtarget.h"
 
 #include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/InitializePasses.h"
 #include "llvm/Target/TargetMachine.h"
 
 using namespace llvm;
 
-#define DEBUG_TYPE "x86-suppress-egpr-and-ndd-for-relocation"
+#define DEBUG_TYPE "x86-suppress-apx-for-relocation"
 
-static cl::opt<bool> X86SuppressEGPRAndNDDForReloc(
+static cl::opt<bool> X86SuppressAPXForReloc(
     DEBUG_TYPE,
-    cl::desc("Suppress EGPR and NDD for instructions with relocations on "
-             "x86-64 ELF"),
+    cl::desc("Suppress APX features (EGPR, NDD and NF) for instructions with "
+             "relocations on x86-64 ELF"),
     cl::init(true));
 
 namespace {
-class X86SuppressEGPRAndNDDForRelocPass : public MachineFunctionPass {
+class X86SuppressAPXForRelocationPass : public MachineFunctionPass {
 public:
-  X86SuppressEGPRAndNDDForRelocPass() : MachineFunctionPass(ID) {}
+  X86SuppressAPXForRelocationPass() : MachineFunctionPass(ID) {}
 
   StringRef getPassName() const override {
-    return "X86 Suppress EGPR and NDD for relocation";
+    return "X86 Suppress APX features for relocation";
   }
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 
-private:
   static char ID;
 };
 } // namespace
 
-char X86SuppressEGPRAndNDDForRelocPass::ID = 0;
+char X86SuppressAPXForRelocationPass::ID = 0;
 
-FunctionPass *llvm::createX86SuppressEGPRAndNDDForRelocPass() {
-  return new X86SuppressEGPRAndNDDForRelocPass();
+INITIALIZE_PASS_BEGIN(X86SuppressAPXForRelocationPass, DEBUG_TYPE,
+                      "X86 Suppress APX features for relocation", false, false)
+INITIALIZE_PASS_END(X86SuppressAPXForRelocationPass, DEBUG_TYPE,
+                    "X86 Suppress APX features for relocation", false, false)
+
+FunctionPass *llvm::createX86SuppressAPXForRelocationPass() {
+  return new X86SuppressAPXForRelocationPass();
 }
 
-static void suppressEGPRRegClass(MachineFunction &MF, MachineInstr &MI) {
+static void suppressEGPRRegClass(MachineFunction &MF, MachineInstr &MI,
+                                 unsigned int OpNum) {
   MachineRegisterInfo *MRI = &MF.getRegInfo();
-  auto Reg = MI.getOperand(0).getReg();
+  auto Reg = MI.getOperand(OpNum).getReg();
   if (!Reg.isVirtual()) {
     assert(!X86II::isApxExtendedReg(Reg) && "APX EGPR is used unexpectedly.");
     return;
@@ -71,10 +79,10 @@ static void suppressEGPRRegClass(MachineFunction &MF, MachineInstr &MI) {
   MRI->setRegClass(Reg, NewRC);
 }
 
-bool X86SuppressEGPRAndNDDForRelocPass::runOnMachineFunction(
+bool X86SuppressAPXForRelocationPass::runOnMachineFunction(
     MachineFunction &MF) {
   if (MF.getTarget().Options.MCOptions.X86APXRelaxRelocations ||
-      !X86SuppressEGPRAndNDDForReloc)
+      !X86SuppressAPXForReloc)
     return false;
   const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
   if (!ST.hasEGPR() && !ST.hasNDD() && !ST.hasNF())
@@ -113,28 +121,48 @@ bool X86SuppressEGPRAndNDDForRelocPass::runOnMachineFunction(
       case X86::XOR64rm: {
         for (auto &MO : MI.operands()) {
           if (MO.getTargetFlags() == X86II::MO_GOTTPOFF ||
-              MO.getTargetFlags() == X86II::MO_GOTPCREL)
-            suppressEGPRRegClass(MF, MI);
+              MO.getTargetFlags() == X86II::MO_GOTPCREL) {
+            suppressEGPRRegClass(MF, MI, 0);
+            break;
+          }
         }
         break;
       }
       case X86::MOV64rm: {
-        if (MI.getOperand(4).getTargetFlags() == X86II::MO_GOTTPOFF)
-          suppressEGPRRegClass(MF, MI);
+        for (auto &MO : MI.operands()) {
+          if (MO.getTargetFlags() == X86II::MO_GOTTPOFF) {
+            suppressEGPRRegClass(MF, MI, 0);
+            break;
+          }
+        }
         break;
       }
       case X86::ADD64rm_NF:
       case X86::ADD64rm_ND:
-      case X86::ADD64mr_ND:
-      case X86::ADD64mr_NF_ND:
       case X86::ADD64rm_NF_ND: {
-        // TODO: implement this if there is a case of NDD/NF instructions with
-        // GOTTPOFF relocation (update the instructions to ADD64rm/ADD64mr and
-        // suppress EGPR)
-        for (auto &MO : MI.operands())
+        for (auto &MO : MI.operands()) {
+          if (MO.getTargetFlags() == X86II::MO_GOTTPOFF) {
+            suppressEGPRRegClass(MF, MI, 0);
+            const MCInstrDesc &NewDesc = ST.getInstrInfo()->get(X86::ADD64rm);
+            MI.setDesc(NewDesc);
+            if (Opcode == X86::ADD64rm_ND || Opcode == X86::ADD64rm_NF_ND) {
+              MI.tieOperands(0, 1);
+              MI.getOperand(1).setIsKill(false);
+              suppressEGPRRegClass(MF, MI, 1);
+            }
+            break;
+          }
+        }
+        break;
+      }
+      case X86::ADD64mr_ND:
+      case X86::ADD64mr_NF_ND: {
+        for ([[maybe_unused]] auto &MO : MI.operands()) {
           assert((MO.getTargetFlags() != X86II::MO_GOTTPOFF) &&
-                 "Suppressing NDD/NF instructions with relocation is "
+                 "Suppressing this instruction with relocation is "
                  "unimplemented!");
+          break;
+        }
         break;
       }
       }

llvm/lib/Target/X86/X86TargetMachine.cpp

@@ -105,6 +105,7 @@ extern "C" LLVM_C_ABI void LLVMInitializeX86Target() {
   initializeX86FixupInstTuningPassPass(PR);
   initializeX86FixupVectorConstantsPassPass(PR);
   initializeX86DynAllocaExpanderPass(PR);
+  initializeX86SuppressAPXForRelocationPassPass(PR);
 }
 
 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
@@ -568,7 +569,7 @@ void X86PassConfig::addPreRegAlloc() {
   else
     addPass(createX86FastPreTileConfigPass());
 
-  addPass(createX86SuppressEGPRAndNDDForRelocPass());
+  addPass(createX86SuppressAPXForRelocationPass());
 }
 
 void X86PassConfig::addMachineSSAOptimization() {

llvm/test/CodeGen/X86/O0-pipeline.ll

@@ -45,7 +45,7 @@
 ; CHECK-NEXT:       X86 EFLAGS copy lowering
 ; CHECK-NEXT:       X86 DynAlloca Expander
 ; CHECK-NEXT:       Fast Tile Register Preconfigure
-; CHECK-NEXT:       X86 Suppress EGPR and NDD for relocation
+; CHECK-NEXT:       X86 Suppress APX features for relocation
 ; CHECK-NEXT:       Eliminate PHI nodes for register allocation
 ; CHECK-NEXT:       Two-Address instruction pass
 ; CHECK-NEXT:       Fast Register Allocator

llvm/test/CodeGen/X86/apx/tls-desc.ll renamed to llvm/test/CodeGen/X86/apx/tls.ll

@@ -18,7 +18,7 @@
 ; RUN: ld.lld  %t.o %t1.o -o %t.so
 ; RUN: llvm-objdump --no-print-imm-hex -dr %t.so | FileCheck %s --check-prefix=GOTTPOFF_LD_NOAPXRELAX
 
-; RUN: llc -mattr=+egpr %s -mtriple=x86_64 -filetype=obj -o %t.o -x86-suppress-egpr-and-ndd-for-relocation=false
+; RUN: llc -mattr=+egpr %s -mtriple=x86_64 -filetype=obj -o %t.o -x86-suppress-apx-for-relocation=false
 ; RUN: llvm-objdump --no-print-imm-hex -dr %t.o | FileCheck %s --check-prefix=GOTTPOFF_NOAPXRELAX_APXINSTR
 ; RUN: echo '.tbss; .globl b,c,d,e,f,g,h,i,j; b: .zero 4;c: .zero 4;d: .zero 4;e: .zero 4;f: .zero 4;g: .zero 4;h: .zero 4;i: .zero 4;j: .zero 4' | llvm-mc -filetype=obj -triple=x86_64 - -o %t1.o
 ; RUN: ld.lld  %t.o %t1.o -o %t.so

llvm/test/CodeGen/X86/opt-pipeline.ll

@@ -133,7 +133,7 @@
 ; CHECK-NEXT:       MachineDominator Tree Construction
 ; CHECK-NEXT:       Machine Natural Loop Construction
 ; CHECK-NEXT:       Tile Register Pre-configure
-; CHECK-NEXT:       X86 Suppress EGPR and NDD for relocation
+; CHECK-NEXT:       X86 Suppress APX features for relocation
 ; CHECK-NEXT:       Detect Dead Lanes
 ; CHECK-NEXT:       Init Undef Pass
 ; CHECK-NEXT:       Process Implicit Definitions