Review comments

Author: easyonaadit

llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

@@ -1192,8 +1192,7 @@ bool AMDGPURegisterBankInfo::applyMappingDynStackAlloc(
 
   if (SizeBank != &AMDGPU::SGPRRegBank) {
     auto WaveReduction =
-        B.buildIntrinsic(Intrinsic::amdgcn_wave_reduce_umax,
-                         {LLT::scalar(MRI.getType(AllocSize).getSizeInBits())})
+        B.buildIntrinsic(Intrinsic::amdgcn_wave_reduce_umax, {LLT::scalar(32)})
             .addUse(AllocSize)
             .addImm(0);
     AllocSize = WaveReduction.getReg(0);

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

@@ -4018,10 +4018,10 @@ SDValue SITargetLowering::LowerCall(CallLoweringInfo &CLI,
 
 // This is similar to the default implementation in ExpandDYNAMIC_STACKALLOC,
 // except for:
-// 1. stack growth direction(default: downwards, AMDGPU: upwards), and
-// 2. scale size where, scale = wave-reduction(alloca-size) * wave-size
-SDValue SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(SDValue Op,
-                                                      SelectionDAG &DAG) const {
+// 1. Stack growth direction(default: downwards, AMDGPU: upwards), and
+// 2. Scale size where, scale = wave-reduction(alloca-size) * wave-size
+SDValue SITargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
+                                                  SelectionDAG &DAG) const {
   const MachineFunction &MF = DAG.getMachineFunction();
   const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
 
@@ -4057,13 +4057,13 @@ SDValue SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(SDValue Op,
   assert(Size.getValueType() == MVT::i32 && "Size must be 32-bit");
   SDValue NewSP;
   if (isa<ConstantSDNode>(Op.getOperand(1))) {
-    // for constant sized alloca, scale alloca size by wave-size
+    // For constant sized alloca, scale alloca size by wave-size
     SDValue ScaledSize = DAG.getNode(
         ISD::SHL, dl, VT, Size,
         DAG.getConstant(Subtarget->getWavefrontSizeLog2(), dl, MVT::i32));
     NewSP = DAG.getNode(ISD::ADD, dl, VT, BaseAddr, ScaledSize); // Value
   } else {
-    // for dynamic sized alloca, perform wave-wide reduction to get max of
+    // For dynamic sized alloca, perform wave-wide reduction to get max of
     // alloca size(divergent) and then scale it by wave-size
     SDValue WaveReduction =
         DAG.getTargetConstant(Intrinsic::amdgcn_wave_reduce_umax, dl, MVT::i32);
@@ -4086,11 +4086,6 @@ SDValue SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(SDValue Op,
   return DAG.getMergeValues({BaseAddr, CallSeqEnd}, dl);
 }
 
-SDValue SITargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
-                                                  SelectionDAG &DAG) const {
-  return lowerDYNAMIC_STACKALLOCImpl(Op, DAG); // Use "generic" expansion.
-}
-
 SDValue SITargetLowering::LowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const {
   if (Op.getValueType() != MVT::i32)
     return Op; // Defer to cannot select error.

llvm/lib/Target/AMDGPU/SIISelLowering.h

@@ -421,7 +421,6 @@ class SITargetLowering final : public AMDGPUTargetLowering {
   SDValue LowerCall(CallLoweringInfo &CLI,
                     SmallVectorImpl<SDValue> &InVals) const override;
 
-  SDValue lowerDYNAMIC_STACKALLOCImpl(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;