1- ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2- ; RUN: llc -mtriple arm-- -mattr=+vfp4 -O0 -o - %s | FileCheck %s
3- ; RUN: llc -mtriple arm-- -mattr=+vfp4 -O3 -o - %s | FileCheck %s --check-prefix=SUBOPTIMAL
4-
1+ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
2+ ; RUN: llc -mtriple armv7-- -mattr=+vfp4 -O0 -o - %s | FileCheck %s
3+ ; RUN: llc -mtriple armv7-- -mattr=+vfp4 -O3 -o - %s | FileCheck %s --check-prefix=CHECK-O3
54
65declare float @llvm.experimental.constrained.sitofp.f32.i32 (i32 , metadata , metadata )
76declare float @llvm.experimental.constrained.sitofp.f32.i16 (i16 , metadata , metadata )
87declare i1 @llvm.experimental.constrained.fcmp.f32 (float , float , metadata , metadata )
98declare float @llvm.experimental.constrained.uitofp.f32.i16 (i16 , metadata , metadata )
109
11- define i32 @test () #0 {
10+ define i32 @test (i32 %a , i16 %b ) #0 {
1211; CHECK-LABEL: test:
1312; CHECK: @ %bb.0: @ %entry
14- ; CHECK-NEXT: sub sp, sp, #8
15- ; CHECK-NEXT: mov r0, #53477376
16- ; CHECK-NEXT: orr r0, r0, #1073741824
17- ; CHECK-NEXT: str r0, [sp, #4]
18- ; CHECK-NEXT: mov r0, #-2147483647
19- ; CHECK-NEXT: str r0, [sp]
13+ ; CHECK-NEXT: sub sp, sp, #16
14+ ; CHECK-NEXT: mov r2, r0
15+ ; CHECK-NEXT: sxth r0, r1
16+ ; CHECK-NEXT: movw r1, #0
17+ ; CHECK-NEXT: movt r1, #17200
18+ ; CHECK-NEXT: str r1, [sp, #4]
19+ ; CHECK-NEXT: eor r2, r2, #-2147483648
20+ ; CHECK-NEXT: str r2, [sp]
2021; CHECK-NEXT: vldr d16, [sp]
2122; CHECK-NEXT: vldr d17, .LCPI0_0
2223; CHECK-NEXT: vsub.f64 d16, d16, d17
2324; CHECK-NEXT: vcvt.f32.f64 s0, d16
24- ; CHECK-NEXT: vcmp.f32 s0, s0
25+ ; CHECK-NEXT: str r1, [sp, #12]
26+ ; CHECK-NEXT: eor r0, r0, #-2147483648
27+ ; CHECK-NEXT: str r0, [sp, #8]
28+ ; CHECK-NEXT: vldr d16, [sp, #8]
29+ ; CHECK-NEXT: vsub.f64 d16, d16, d17
30+ ; CHECK-NEXT: vcvt.f32.f64 s2, d16
31+ ; CHECK-NEXT: vcmp.f32 s0, s2
2532; CHECK-NEXT: vmrs APSR_nzcv, fpscr
2633; CHECK-NEXT: mov r0, #0
27- ; CHECK-NEXT: moveq r0, #1
28- ; CHECK-NEXT: add sp, sp, #8
29- ; CHECK-NEXT: mov pc, lr
34+ ; CHECK-NEXT: movweq r0, #1
35+ ; CHECK-NEXT: add sp, sp, #16
36+ ; CHECK-NEXT: bx lr
3037; CHECK-NEXT: .p2align 3
3138; CHECK-NEXT: @ %bb.1:
3239; CHECK-NEXT: .LCPI0_0:
3340; CHECK-NEXT: .long 2147483648 @ double 4503601774854144
3441; CHECK-NEXT: .long 1127219200
3542;
36- ; SUBOPTIMAL-LABEL: test:
37- ; SUBOPTIMAL: @ %bb.0: @ %entry
38- ; SUBOPTIMAL-NEXT: sub sp, sp, #8
39- ; SUBOPTIMAL-NEXT: mov r0, #53477376
40- ; SUBOPTIMAL-NEXT: orr r0, r0, #1073741824
41- ; SUBOPTIMAL-NEXT: str r0, [sp, #4]
42- ; SUBOPTIMAL-NEXT: mov r0, #-2147483647
43- ; SUBOPTIMAL-NEXT: str r0, [sp]
44- ; SUBOPTIMAL-NEXT: vldr d16, [sp]
45- ; SUBOPTIMAL-NEXT: vldr d17, .LCPI0_0
46- ; SUBOPTIMAL-NEXT: vsub.f64 d16, d16, d17
47- ; SUBOPTIMAL-NEXT: vcvt.f32.f64 s0, d16
48- ; SUBOPTIMAL-NEXT: vcmp.f32 s0, s0
49- ; SUBOPTIMAL-NEXT: vmrs APSR_nzcv, fpscr
50- ; SUBOPTIMAL-NEXT: mov r0, #0
51- ; SUBOPTIMAL-NEXT: moveq r0, #1
52- ; SUBOPTIMAL-NEXT: add sp, sp, #8
53- ; SUBOPTIMAL-NEXT: mov pc, lr
54- ; SUBOPTIMAL-NEXT: .p2align 3
55- ; SUBOPTIMAL-NEXT: @ %bb.1:
56- ; SUBOPTIMAL-NEXT: .LCPI0_0:
57- ; SUBOPTIMAL-NEXT: .long 2147483648 @ double 4503601774854144
58- ; SUBOPTIMAL-NEXT: .long 1127219200
43+ ; CHECK-O3-LABEL: test:
44+ ; CHECK-O3: @ %bb.0: @ %entry
45+ ; CHECK-O3-NEXT: sub sp, sp, #16
46+ ; CHECK-O3-NEXT: sxth r1, r1
47+ ; CHECK-O3-NEXT: movw r2, #0
48+ ; CHECK-O3-NEXT: movt r2, #17200
49+ ; CHECK-O3-NEXT: str r2, [sp, #4]
50+ ; CHECK-O3-NEXT: eor r0, r0, #-2147483648
51+ ; CHECK-O3-NEXT: str r0, [sp]
52+ ; CHECK-O3-NEXT: vldr d16, [sp]
53+ ; CHECK-O3-NEXT: vldr d17, .LCPI0_0
54+ ; CHECK-O3-NEXT: vsub.f64 d16, d16, d17
55+ ; CHECK-O3-NEXT: vcvt.f32.f64 s0, d16
56+ ; CHECK-O3-NEXT: str r2, [sp, #12]
57+ ; CHECK-O3-NEXT: eor r0, r1, #-2147483648
58+ ; CHECK-O3-NEXT: str r0, [sp, #8]
59+ ; CHECK-O3-NEXT: vldr d16, [sp, #8]
60+ ; CHECK-O3-NEXT: vsub.f64 d16, d16, d17
61+ ; CHECK-O3-NEXT: vcvt.f32.f64 s2, d16
62+ ; CHECK-O3-NEXT: vcmp.f32 s0, s2
63+ ; CHECK-O3-NEXT: vmrs APSR_nzcv, fpscr
64+ ; CHECK-O3-NEXT: mov r0, #0
65+ ; CHECK-O3-NEXT: movweq r0, #1
66+ ; CHECK-O3-NEXT: add sp, sp, #16
67+ ; CHECK-O3-NEXT: bx lr
68+ ; CHECK-O3-NEXT: .p2align 3
69+ ; CHECK-O3-NEXT: @ %bb.1:
70+ ; CHECK-O3-NEXT: .LCPI0_0:
71+ ; CHECK-O3-NEXT: .long 2147483648 @ double 4503601774854144
72+ ; CHECK-O3-NEXT: .long 1127219200
5973entry:
60- %conv = call float @llvm.experimental.constrained.sitofp.f32.i32 (i32 1 , metadata !"round.tonearest" , metadata !"fpexcept.strict" ) #1
61- %conv1 = call float @llvm.experimental.constrained.sitofp.f32.i16 (i16 1 , metadata !"round.tonearest" , metadata !"fpexcept.strict" ) #1
74+ %conv = call float @llvm.experimental.constrained.sitofp.f32.i32 (i32 %a , metadata !"round.tonearest" , metadata !"fpexcept.strict" ) #1
75+ %conv1 = call float @llvm.experimental.constrained.sitofp.f32.i16 (i16 %b , metadata !"round.tonearest" , metadata !"fpexcept.strict" ) #1
6276 %cmp = call i1 @llvm.experimental.constrained.fcmp.f32 (float %conv , float %conv1 , metadata !"oeq" , metadata !"fpexcept.strict" ) #1
6377 %conv2 = zext i1 %cmp to i32
6478 ret i32 %conv2
6579}
6680
67- define i32 @test2 () #0 {
81+ define i32 @test2 (i32 %a , i16 %b ) #0 {
6882; CHECK-LABEL: test2:
6983; CHECK: @ %bb.0: @ %entry
7084; CHECK-NEXT: sub sp, sp, #16
71- ; CHECK-NEXT: mov r0, #53477376
72- ; CHECK-NEXT: orr r0, r0, #1073741824
73- ; CHECK-NEXT: str r0, [sp, #12]
74- ; CHECK-NEXT: mov r1, #-2147483647
75- ; CHECK-NEXT: str r1, [sp, #8]
76- ; CHECK-NEXT: vldr d16, [sp, #8]
85+ ; CHECK-NEXT: mov r2, r0
86+ ; CHECK-NEXT: uxth r0, r1
87+ ; CHECK-NEXT: movw r1, #0
88+ ; CHECK-NEXT: movt r1, #17200
89+ ; CHECK-NEXT: str r1, [sp, #4]
90+ ; CHECK-NEXT: eor r2, r2, #-2147483648
91+ ; CHECK-NEXT: str r2, [sp]
92+ ; CHECK-NEXT: vldr d16, [sp]
7793; CHECK-NEXT: vldr d17, .LCPI1_0
7894; CHECK-NEXT: vsub.f64 d16, d16, d17
7995; CHECK-NEXT: vcvt.f32.f64 s0, d16
80- ; CHECK-NEXT: str r0, [sp, #4]
81- ; CHECK-NEXT: mov r0, #1
82- ; CHECK-NEXT: str r0, [sp]
83- ; CHECK-NEXT: vldr d16, [sp]
96+ ; CHECK-NEXT: str r1, [sp, #12]
97+ ; CHECK-NEXT: str r0, [sp, #8]
98+ ; CHECK-NEXT: vldr d16, [sp, #8]
8499; CHECK-NEXT: vldr d17, .LCPI1_1
85100; CHECK-NEXT: vsub.f64 d16, d16, d17
86101; CHECK-NEXT: vcvt.f32.f64 s2, d16
87102; CHECK-NEXT: vcmp.f32 s0, s2
88103; CHECK-NEXT: vmrs APSR_nzcv, fpscr
89104; CHECK-NEXT: mov r0, #0
90- ; CHECK-NEXT: moveq r0, #1
105+ ; CHECK-NEXT: movweq r0, #1
91106; CHECK-NEXT: add sp, sp, #16
92- ; CHECK-NEXT: mov pc, lr
107+ ; CHECK-NEXT: bx lr
93108; CHECK-NEXT: .p2align 3
94109; CHECK-NEXT: @ %bb.1:
95110; CHECK-NEXT: .LCPI1_0:
@@ -99,42 +114,42 @@ define i32 @test2() #0 {
99114; CHECK-NEXT: .long 0 @ double 4503599627370496
100115; CHECK-NEXT: .long 1127219200
101116;
102- ; SUBOPTIMAL -LABEL: test2:
103- ; SUBOPTIMAL : @ %bb.0: @ %entry
104- ; SUBOPTIMAL -NEXT: sub sp, sp, #16
105- ; SUBOPTIMAL- NEXT: mov r0, #53477376
106- ; SUBOPTIMAL- NEXT: orr r0, r0, #1073741824
107- ; SUBOPTIMAL- NEXT: str r0, [sp, #12]
108- ; SUBOPTIMAL- NEXT: mov r1, #-2147483647
109- ; SUBOPTIMAL- NEXT: str r1, [sp , #8]
110- ; SUBOPTIMAL- NEXT: vldr d16 , [sp, #8 ]
111- ; SUBOPTIMAL- NEXT: vldr d17, .LCPI1_0
112- ; SUBOPTIMAL- NEXT: vsub.f64 d16, d16, d17
113- ; SUBOPTIMAL- NEXT: vcvt.f32. f64 s0 , d16
114- ; SUBOPTIMAL- NEXT: str r0, [sp, #4]
115- ; SUBOPTIMAL- NEXT: mov r0, #1
116- ; SUBOPTIMAL- NEXT: str r0 , [sp]
117- ; SUBOPTIMAL- NEXT: vldr d16, [sp]
118- ; SUBOPTIMAL -NEXT: vldr d17, .LCPI1_1
119- ; SUBOPTIMAL -NEXT: vsub.f64 d16, d16, d17
120- ; SUBOPTIMAL -NEXT: vcvt.f32.f64 s2, d16
121- ; SUBOPTIMAL -NEXT: vcmp.f32 s0, s2
122- ; SUBOPTIMAL -NEXT: vmrs APSR_nzcv, fpscr
123- ; SUBOPTIMAL -NEXT: mov r0, #0
124- ; SUBOPTIMAL- NEXT: moveq r0, #1
125- ; SUBOPTIMAL -NEXT: add sp, sp, #16
126- ; SUBOPTIMAL- NEXT: mov pc, lr
127- ; SUBOPTIMAL -NEXT: .p2align 3
128- ; SUBOPTIMAL -NEXT: @ %bb.1:
129- ; SUBOPTIMAL -NEXT: .LCPI1_0:
130- ; SUBOPTIMAL -NEXT: .long 2147483648 @ double 4503601774854144
131- ; SUBOPTIMAL -NEXT: .long 1127219200
132- ; SUBOPTIMAL -NEXT: .LCPI1_1:
133- ; SUBOPTIMAL -NEXT: .long 0 @ double 4503599627370496
134- ; SUBOPTIMAL -NEXT: .long 1127219200
117+ ; CHECK-O3 -LABEL: test2:
118+ ; CHECK-O3 : @ %bb.0: @ %entry
119+ ; CHECK-O3 -NEXT: sub sp, sp, #16
120+ ; CHECK-O3- NEXT: uxth r1, r1
121+ ; CHECK-O3- NEXT: movw r2, #0
122+ ; CHECK-O3- NEXT: movt r2, #17200
123+ ; CHECK-O3- NEXT: str r2, [sp, #4]
124+ ; CHECK-O3- NEXT: eor r0, r0 , #-2147483648
125+ ; CHECK-O3- NEXT: str r0 , [sp]
126+ ; CHECK-O3- NEXT: vldr d16, [sp]
127+ ; CHECK-O3- NEXT: vldr d17, .LCPI1_0
128+ ; CHECK-O3- NEXT: vsub. f64 d16 , d16, d17
129+ ; CHECK-O3- NEXT: vcvt.f32.f64 s0, d16
130+ ; CHECK-O3- NEXT: str r2, [sp, #12]
131+ ; CHECK-O3- NEXT: str r1 , [sp, #8 ]
132+ ; CHECK-O3- NEXT: vldr d16, [sp, #8 ]
133+ ; CHECK-O3 -NEXT: vldr d17, .LCPI1_1
134+ ; CHECK-O3 -NEXT: vsub.f64 d16, d16, d17
135+ ; CHECK-O3 -NEXT: vcvt.f32.f64 s2, d16
136+ ; CHECK-O3 -NEXT: vcmp.f32 s0, s2
137+ ; CHECK-O3 -NEXT: vmrs APSR_nzcv, fpscr
138+ ; CHECK-O3 -NEXT: mov r0, #0
139+ ; CHECK-O3- NEXT: movweq r0, #1
140+ ; CHECK-O3 -NEXT: add sp, sp, #16
141+ ; CHECK-O3- NEXT: bx lr
142+ ; CHECK-O3 -NEXT: .p2align 3
143+ ; CHECK-O3 -NEXT: @ %bb.1:
144+ ; CHECK-O3 -NEXT: .LCPI1_0:
145+ ; CHECK-O3 -NEXT: .long 2147483648 @ double 4503601774854144
146+ ; CHECK-O3 -NEXT: .long 1127219200
147+ ; CHECK-O3 -NEXT: .LCPI1_1:
148+ ; CHECK-O3 -NEXT: .long 0 @ double 4503599627370496
149+ ; CHECK-O3 -NEXT: .long 1127219200
135150entry:
136- %conv = call float @llvm.experimental.constrained.sitofp.f32.i32 (i32 1 , metadata !"round.tonearest" , metadata !"fpexcept.strict" ) #1
137- %conv1 = call float @llvm.experimental.constrained.uitofp.f32.i16 (i16 1 , metadata !"round.tonearest" , metadata !"fpexcept.strict" ) #1
151+ %conv = call float @llvm.experimental.constrained.sitofp.f32.i32 (i32 %a , metadata !"round.tonearest" , metadata !"fpexcept.strict" ) #1
152+ %conv1 = call float @llvm.experimental.constrained.uitofp.f32.i16 (i16 %b , metadata !"round.tonearest" , metadata !"fpexcept.strict" ) #1
138153 %cmp = call i1 @llvm.experimental.constrained.fcmp.f32 (float %conv , float %conv1 , metadata !"oeq" , metadata !"fpexcept.strict" ) #1
139154 %conv2 = zext i1 %cmp to i32
140155 ret i32 %conv2
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