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[llvm][RISCV] Support P extension CodeGen (#167882)
This patch support PADD_W, PSUB_W, PSADD_W, PSADDU_W, PSSUB_W, PSSUBU_W, PAADD_W and PAADDU_W
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‎llvm/lib/Target/RISCV/RISCVInstrInfoP.td‎

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@@ -1539,6 +1539,20 @@ let Predicates = [HasStdExtP, IsRV64] in {
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// 32-bit PLI SD node pattern
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def: Pat<(v2i32 (riscv_pli simm10:$imm10)), (PLI_W simm10:$imm10)>;
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// Basic 32-bit arithmetic patterns
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def: Pat<(v2i32 (add GPR:$rs1, GPR:$rs2)), (PADD_W GPR:$rs1, GPR:$rs2)>;
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def: Pat<(v2i32 (sub GPR:$rs1, GPR:$rs2)), (PSUB_W GPR:$rs1, GPR:$rs2)>;
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// 32-bit saturating add/sub patterns
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def: Pat<(v2i32 (saddsat GPR:$rs1, GPR:$rs2)), (PSADD_W GPR:$rs1, GPR:$rs2)>;
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def: Pat<(v2i32 (uaddsat GPR:$rs1, GPR:$rs2)), (PSADDU_W GPR:$rs1, GPR:$rs2)>;
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def: Pat<(v2i32 (ssubsat GPR:$rs1, GPR:$rs2)), (PSSUB_W GPR:$rs1, GPR:$rs2)>;
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def: Pat<(v2i32 (usubsat GPR:$rs1, GPR:$rs2)), (PSSUBU_W GPR:$rs1, GPR:$rs2)>;
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// 32-bit averaging patterns
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def: Pat<(v2i32 (avgfloors GPR:$rs1, GPR:$rs2)), (PAADD_W GPR:$rs1, GPR:$rs2)>;
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def: Pat<(v2i32 (avgflooru GPR:$rs1, GPR:$rs2)), (PAADDU_W GPR:$rs1, GPR:$rs2)>;
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// 32-bit averaging-sub patterns
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def: Pat<(v2i32 (riscv_pasub GPR:$rs1, GPR:$rs2)), (PASUB_W GPR:$rs1, GPR:$rs2)>;
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def: Pat<(v2i32 (riscv_pasubu GPR:$rs1, GPR:$rs2)), (PASUBU_W GPR:$rs1, GPR:$rs2)>;

‎llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll‎

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@@ -495,6 +495,182 @@ define void @test_extract_vector_32(ptr %ret_ptr, ptr %a_ptr) {
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ret void
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}
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; Test basic add/sub operations for v2i32 (RV64 only)
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define void @test_padd_w(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) {
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; CHECK-LABEL: test_padd_w:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ld a1, 0(a1)
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; CHECK-NEXT: ld a2, 0(a2)
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; CHECK-NEXT: padd.w a1, a1, a2
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; CHECK-NEXT: sd a1, 0(a0)
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; CHECK-NEXT: ret
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%a = load <2 x i32>, ptr %a_ptr
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%b = load <2 x i32>, ptr %b_ptr
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%res = add <2 x i32> %a, %b
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store <2 x i32> %res, ptr %ret_ptr
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ret void
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}
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define void @test_psub_w(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) {
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; CHECK-LABEL: test_psub_w:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ld a1, 0(a1)
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; CHECK-NEXT: ld a2, 0(a2)
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; CHECK-NEXT: psub.w a1, a1, a2
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; CHECK-NEXT: sd a1, 0(a0)
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; CHECK-NEXT: ret
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%a = load <2 x i32>, ptr %a_ptr
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%b = load <2 x i32>, ptr %b_ptr
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%res = sub <2 x i32> %a, %b
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store <2 x i32> %res, ptr %ret_ptr
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ret void
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}
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; Test saturating add operations for v2i32 (RV64 only)
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define void @test_psadd_w(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) {
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; CHECK-LABEL: test_psadd_w:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ld a1, 0(a1)
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; CHECK-NEXT: ld a2, 0(a2)
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; CHECK-NEXT: psadd.w a1, a1, a2
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; CHECK-NEXT: sd a1, 0(a0)
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; CHECK-NEXT: ret
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%a = load <2 x i32>, ptr %a_ptr
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%b = load <2 x i32>, ptr %b_ptr
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%res = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> %a, <2 x i32> %b)
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store <2 x i32> %res, ptr %ret_ptr
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ret void
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}
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define void @test_psaddu_w(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) {
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; CHECK-LABEL: test_psaddu_w:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ld a1, 0(a1)
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; CHECK-NEXT: ld a2, 0(a2)
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; CHECK-NEXT: psaddu.w a1, a1, a2
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; CHECK-NEXT: sd a1, 0(a0)
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; CHECK-NEXT: ret
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%a = load <2 x i32>, ptr %a_ptr
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%b = load <2 x i32>, ptr %b_ptr
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%res = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %a, <2 x i32> %b)
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store <2 x i32> %res, ptr %ret_ptr
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ret void
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}
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; Test saturating sub operations for v2i32 (RV64 only)
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define void @test_pssub_w(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) {
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; CHECK-LABEL: test_pssub_w:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ld a1, 0(a1)
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; CHECK-NEXT: ld a2, 0(a2)
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; CHECK-NEXT: pssub.w a1, a1, a2
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; CHECK-NEXT: sd a1, 0(a0)
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; CHECK-NEXT: ret
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%a = load <2 x i32>, ptr %a_ptr
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%b = load <2 x i32>, ptr %b_ptr
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%res = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %a, <2 x i32> %b)
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store <2 x i32> %res, ptr %ret_ptr
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ret void
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}
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define void @test_pssubu_w(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) {
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; CHECK-LABEL: test_pssubu_w:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ld a1, 0(a1)
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; CHECK-NEXT: ld a2, 0(a2)
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; CHECK-NEXT: pssubu.w a1, a1, a2
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; CHECK-NEXT: sd a1, 0(a0)
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; CHECK-NEXT: ret
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%a = load <2 x i32>, ptr %a_ptr
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%b = load <2 x i32>, ptr %b_ptr
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%res = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %a, <2 x i32> %b)
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store <2 x i32> %res, ptr %ret_ptr
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ret void
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}
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; Test averaging floor signed operations for v2i32 (RV64 only)
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; avgfloors pattern: (a + b) arithmetic shift right 1
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define void @test_paadd_w(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) {
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; CHECK-LABEL: test_paadd_w:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ld a1, 0(a1)
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; CHECK-NEXT: ld a2, 0(a2)
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; CHECK-NEXT: paadd.w a1, a1, a2
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; CHECK-NEXT: sd a1, 0(a0)
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; CHECK-NEXT: ret
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%a = load <2 x i32>, ptr %a_ptr
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%b = load <2 x i32>, ptr %b_ptr
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%ext.a = sext <2 x i32> %a to <2 x i64>
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%ext.b = sext <2 x i32> %b to <2 x i64>
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%add = add nsw <2 x i64> %ext.a, %ext.b
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%shift = ashr <2 x i64> %add, <i64 1, i64 1>
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%res = trunc <2 x i64> %shift to <2 x i32>
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store <2 x i32> %res, ptr %ret_ptr
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ret void
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}
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; Test averaging floor unsigned operations for v2i32 (RV64 only)
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; avgflooru pattern: (a & b) + ((a ^ b) >> 1)
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define void @test_paaddu_w(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) {
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; CHECK-LABEL: test_paaddu_w:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ld a1, 0(a1)
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; CHECK-NEXT: ld a2, 0(a2)
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; CHECK-NEXT: paaddu.w a1, a1, a2
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; CHECK-NEXT: sd a1, 0(a0)
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; CHECK-NEXT: ret
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%a = load <2 x i32>, ptr %a_ptr
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%b = load <2 x i32>, ptr %b_ptr
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%and = and <2 x i32> %a, %b
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%xor = xor <2 x i32> %a, %b
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%shift = lshr <2 x i32> %xor, <i32 1, i32 1>
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%res = add <2 x i32> %and, %shift
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store <2 x i32> %res, ptr %ret_ptr
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ret void
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}
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; Test averaging floor subtraction signed for v2i32 (RV64 only)
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; pasub pattern: (a - b) arithmetic shift right 1
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define void @test_pasub_w(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) {
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; CHECK-LABEL: test_pasub_w:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ld a1, 0(a1)
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; CHECK-NEXT: ld a2, 0(a2)
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; CHECK-NEXT: pasub.w a1, a1, a2
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; CHECK-NEXT: sd a1, 0(a0)
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; CHECK-NEXT: ret
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%a = load <2 x i32>, ptr %a_ptr
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%b = load <2 x i32>, ptr %b_ptr
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%a_ext = sext <2 x i32> %a to <2 x i64>
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%b_ext = sext <2 x i32> %b to <2 x i64>
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%sub = sub <2 x i64> %a_ext, %b_ext
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%res = ashr <2 x i64> %sub, <i64 1, i64 1>
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%res_trunc = trunc <2 x i64> %res to <2 x i32>
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store <2 x i32> %res_trunc, ptr %ret_ptr
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ret void
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}
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; Test averaging floor subtraction unsigned for v2i32 (RV64 only)
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; pasubu pattern: (a - b) logical shift right 1
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define void @test_pasubu_w(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) {
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; CHECK-LABEL: test_pasubu_w:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ld a1, 0(a1)
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; CHECK-NEXT: ld a2, 0(a2)
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; CHECK-NEXT: pasubu.w a1, a1, a2
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; CHECK-NEXT: sd a1, 0(a0)
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; CHECK-NEXT: ret
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%a = load <2 x i32>, ptr %a_ptr
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%b = load <2 x i32>, ptr %b_ptr
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%a_ext = zext <2 x i32> %a to <2 x i64>
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%b_ext = zext <2 x i32> %b to <2 x i64>
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%sub = sub <2 x i64> %a_ext, %b_ext
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%res = lshr <2 x i64> %sub, <i64 1, i64 1>
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%res_trunc = trunc <2 x i64> %res to <2 x i32>
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store <2 x i32> %res_trunc, ptr %ret_ptr
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ret void
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}
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; Intrinsic declarations
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declare <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16>, <4 x i16>)
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declare <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16>, <4 x i16>)

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