For truncation from f128 to f16, always use the lib fucntion (direct conversion) instead of HW instructions (stepwise conversion).

Author: esmeyi

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

@@ -223,25 +223,25 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
   }
 
+  setTruncStoreAction(MVT::f128, MVT::f16, Expand);
+  setOperationAction(ISD::FP_TO_FP16, MVT::f128, Expand);
+
   if (Subtarget.isISA3_0()) {
     setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f16, Legal);
     setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Legal);
     setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Legal);
-    setTruncStoreAction(MVT::f128, MVT::f16, Legal);
     setTruncStoreAction(MVT::f64, MVT::f16, Legal);
     setTruncStoreAction(MVT::f32, MVT::f16, Legal);
   } else {
     // No extending loads from f16 or HW conversions back and forth.
     setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f16, Expand);
     setOperationAction(ISD::FP16_TO_FP, MVT::f128, Expand);
-    setOperationAction(ISD::FP_TO_FP16, MVT::f128, Expand);
     setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
     setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
     setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
     setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
     setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
     setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
-    setTruncStoreAction(MVT::f128, MVT::f16, Expand);
     setTruncStoreAction(MVT::f64, MVT::f16, Expand);
     setTruncStoreAction(MVT::f32, MVT::f16, Expand);
   }

llvm/lib/Target/PowerPC/PPCInstrVSX.td

@@ -3997,8 +3997,6 @@ defm : ScalToVecWPermute<
 // Load/convert and convert/store patterns for f16.
 def : Pat<(f128 (extloadf16 ForceXForm:$src)),
           (f128 (XSCVDPQP (XSCVHPDP (LXSIHZX ForceXForm:$src))))>;
-def : Pat<(truncstoref16 f128:$src, ForceXForm:$dst),
-          (STXSIHX (XSCVDPHP (XSCVQPDP $src)), ForceXForm:$dst)>;
 def : Pat<(f64 (extloadf16 ForceXForm:$src)),
           (f64 (XSCVHPDP (LXSIHZX ForceXForm:$src)))>;
 def : Pat<(truncstoref16 f64:$src, ForceXForm:$dst),
@@ -4016,8 +4014,6 @@ def : Pat<(f32 (f16_to_fp i32:$A)),
 def : Pat<(i32 (fp_to_f16 f32:$A)),
           (i32 (MFVSRWZ (XSCVDPHP (COPY_TO_REGCLASS $A, VSFRC))))>;
 def : Pat<(i32 (fp_to_f16 f64:$A)), (i32 (MFVSRWZ (XSCVDPHP $A)))>;
-def : Pat<(i32 (fp_to_f16 f128:$A)),
-          (i32 (MFVSRWZ (XSCVDPHP (XSCVQPDP $A))))>;
 
 // Vector sign extensions
 def : Pat<(f64 (PPCVexts f64:$A, 1)),

llvm/test/CodeGen/PowerPC/f16-to-from-f128.ll

@@ -28,12 +28,19 @@ define half @trunc(fp128 %a) unnamed_addr {
 ;
 ; CHECK-LABEL: trunc:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xscvqpdp v2, v2
-; CHECK-NEXT:    xscvdphp f0, vs34
-; CHECK-NEXT:    mffprwz r3, f0
+; CHECK-NEXT:    mflr r0
+; CHECK-NEXT:    stdu r1, -32(r1)
+; CHECK-NEXT:    std r0, 48(r1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-NEXT:    .cfi_offset lr, 16
+; CHECK-NEXT:    bl __trunctfhf2
+; CHECK-NEXT:    nop
 ; CHECK-NEXT:    clrlwi r3, r3, 16
 ; CHECK-NEXT:    mtfprwz f0, r3
 ; CHECK-NEXT:    xscvhpdp f1, f0
+; CHECK-NEXT:    addi r1, r1, 32
+; CHECK-NEXT:    ld r0, 16(r1)
+; CHECK-NEXT:    mtlr r0
 ; CHECK-NEXT:    blr
 ;
 ; SOFT-LABEL: trunc: