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Enhance RISCV machine outlining to support a tailcall strategy.
This is modeled on the equivalent path in the AArch64 backend. Whenever the outlining candidate ends in a terminator, we can use a tail call to reach it, removing the need to use a link register or to insert a return instruction in the outlined function. This improves code size in a size-optimized build of an internal benchmark by approximately 3%.
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+175
-95
lines changed

7 files changed

+175
-95
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp‎

Lines changed: 81 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -2925,9 +2925,42 @@ bool RISCVInstrInfo::isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,
29252925
return TargetInstrInfo::isMBBSafeToOutlineFrom(MBB, Flags);
29262926
}
29272927

2928-
// Enum values indicating how an outlined call should be constructed.
2928+
/// Constants defining how certain sequences should be outlined.
2929+
/// This encompasses how an outlined function should be called, and what kind of
2930+
/// frame should be emitted for that outlined function.
2931+
///
2932+
/// \p MachineOutlinerCallViaX5 implies that the function should be called with
2933+
/// using X5 as an alternative link register.
2934+
///
2935+
/// That is,
2936+
///
2937+
/// I1 Materialize addr in X5 OUTLINED_FUNCTION:
2938+
/// I2 --> JAL X5 I1
2939+
/// I3 I2
2940+
/// I3
2941+
/// RET X5
2942+
///
2943+
/// * Call construction overhead: 2 insns
2944+
/// * Frame construction overhead: 1 (ret)
2945+
/// * Requires stack fixups? No
2946+
///
2947+
/// \p MachineOutlinerTailCall implies that the function is being created from
2948+
/// a sequence of instructions ending in a return.
2949+
///
2950+
/// That is,
2951+
///
2952+
/// I1 OUTLINED_FUNCTION:
2953+
/// I2 --> B OUTLINED_FUNCTION I1
2954+
/// RET I2
2955+
/// RET
2956+
///
2957+
/// * Call construction overhead: 2 insns
2958+
/// * Frame construction overhead: 0 (Return included in sequence)
2959+
/// * Requires stack fixups? No
2960+
///
29292961
enum MachineOutlinerConstructionID {
2930-
MachineOutlinerDefault
2962+
MachineOutlinerCallViaX5,
2963+
MachineOutlinerTailCall
29312964
};
29322965

29332966
bool RISCVInstrInfo::shouldOutlineFromFunctionByDefault(
@@ -2941,14 +2974,33 @@ RISCVInstrInfo::getOutliningCandidateInfo(
29412974
std::vector<outliner::Candidate> &RepeatedSequenceLocs,
29422975
unsigned MinRepeats) const {
29432976

2944-
// First we need to filter out candidates where the X5 register (IE t0) can't
2945-
// be used to setup the function call.
2946-
auto CannotInsertCall = [](outliner::Candidate &C) {
2947-
const TargetRegisterInfo *TRI = C.getMF()->getSubtarget().getRegisterInfo();
2948-
return !C.isAvailableAcrossAndOutOfSeq(RISCV::X5, *TRI);
2949-
};
2977+
// If the last instruction in any candidate is a terminator, then we should
2978+
// tail call all of the candidates.
2979+
bool IsTailCall = RepeatedSequenceLocs[0].back().isTerminator();
2980+
2981+
if (!IsTailCall) {
2982+
// Filter out candidates where the X5 register (IE t0) can't
2983+
// be used to setup the function call.
2984+
auto CannotInsertCall = [](outliner::Candidate &C) {
2985+
const TargetRegisterInfo *TRI =
2986+
C.getMF()->getSubtarget().getRegisterInfo();
2987+
if (!C.isAvailableAcrossAndOutOfSeq(RISCV::X5, *TRI))
2988+
return true;
29502989

2951-
llvm::erase_if(RepeatedSequenceLocs, CannotInsertCall);
2990+
// Don't allow modifying the X5 register which we use for return addresses
2991+
// for these outlined functions.
2992+
for (const auto &MI : C) {
2993+
// FIXME: Why is this case not handled by isAvailableAcrossAndOutOfSeq
2994+
// above?
2995+
if (MI.modifiesRegister(RISCV::X5, TRI))
2996+
return true;
2997+
}
2998+
2999+
return false;
3000+
};
3001+
3002+
llvm::erase_if(RepeatedSequenceLocs, CannotInsertCall);
3003+
}
29523004

29533005
// If the sequence doesn't have enough candidates left, then we're done.
29543006
if (RepeatedSequenceLocs.size() < MinRepeats)
@@ -2961,8 +3013,12 @@ RISCVInstrInfo::getOutliningCandidateInfo(
29613013

29623014
// call t0, function = 8 bytes.
29633015
unsigned CallOverhead = 8;
3016+
3017+
MachineOutlinerConstructionID OutlinerType =
3018+
IsTailCall ? MachineOutlinerTailCall : MachineOutlinerCallViaX5;
3019+
29643020
for (auto &C : RepeatedSequenceLocs)
2965-
C.setCallInfo(MachineOutlinerDefault, CallOverhead);
3021+
C.setCallInfo(OutlinerType, CallOverhead);
29663022

29673023
// jr t0 = 4 bytes, 2 bytes if compressed instructions are enabled.
29683024
unsigned FrameOverhead = 4;
@@ -2972,19 +3028,19 @@ RISCVInstrInfo::getOutliningCandidateInfo(
29723028
.hasStdExtCOrZca())
29733029
FrameOverhead = 2;
29743030

3031+
// There is no overhead in the frame when doing a tail call.
3032+
if (IsTailCall)
3033+
FrameOverhead = 0;
3034+
29753035
return std::make_unique<outliner::OutlinedFunction>(
2976-
RepeatedSequenceLocs, SequenceSize, FrameOverhead,
2977-
MachineOutlinerDefault);
3036+
RepeatedSequenceLocs, SequenceSize, FrameOverhead, OutlinerType);
29783037
}
29793038

29803039
outliner::InstrType
29813040
RISCVInstrInfo::getOutliningTypeImpl(const MachineModuleInfo &MMI,
29823041
MachineBasicBlock::iterator &MBBI,
29833042
unsigned Flags) const {
29843043
MachineInstr &MI = *MBBI;
2985-
MachineBasicBlock *MBB = MI.getParent();
2986-
const TargetRegisterInfo *TRI =
2987-
MBB->getParent()->getSubtarget().getRegisterInfo();
29883044
const auto &F = MI.getMF()->getFunction();
29893045

29903046
// We can manually strip out CFI instructions later.
@@ -2995,17 +3051,6 @@ RISCVInstrInfo::getOutliningTypeImpl(const MachineModuleInfo &MMI,
29953051
return F.needsUnwindTableEntry() ? outliner::InstrType::Illegal
29963052
: outliner::InstrType::Invisible;
29973053

2998-
// We need support for tail calls to outlined functions before return
2999-
// statements can be allowed.
3000-
if (MI.isReturn())
3001-
return outliner::InstrType::Illegal;
3002-
3003-
// Don't allow modifying the X5 register which we use for return addresses for
3004-
// these outlined functions.
3005-
if (MI.modifiesRegister(RISCV::X5, TRI) ||
3006-
MI.getDesc().hasImplicitDefOfPhysReg(RISCV::X5))
3007-
return outliner::InstrType::Illegal;
3008-
30093054
// Make sure the operands don't reference something unsafe.
30103055
for (const auto &MO : MI.operands()) {
30113056

@@ -3041,6 +3086,9 @@ void RISCVInstrInfo::buildOutlinedFrame(
30413086

30423087
MBB.addLiveIn(RISCV::X5);
30433088

3089+
if (OF.FrameConstructionID == MachineOutlinerTailCall)
3090+
return;
3091+
30443092
// Add in a return instruction to the end of the outlined frame.
30453093
MBB.insert(MBB.end(), BuildMI(MF, DebugLoc(), get(RISCV::JALR))
30463094
.addReg(RISCV::X0, RegState::Define)
@@ -3052,6 +3100,13 @@ MachineBasicBlock::iterator RISCVInstrInfo::insertOutlinedCall(
30523100
Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It,
30533101
MachineFunction &MF, outliner::Candidate &C) const {
30543102

3103+
if (C.CallConstructionID == MachineOutlinerTailCall) {
3104+
It = MBB.insert(It, BuildMI(MF, DebugLoc(), get(RISCV::PseudoTAIL))
3105+
.addGlobalAddress(M.getNamedValue(MF.getName()), 0,
3106+
RISCVII::MO_CALL));
3107+
return It;
3108+
}
3109+
30553110
// Add in a call instruction to the outlined function at the given location.
30563111
It = MBB.insert(It,
30573112
BuildMI(MF, DebugLoc(), get(RISCV::PseudoCALLReg), RISCV::X5)

‎llvm/test/CodeGen/RISCV/machine-outliner-cfi.mir‎

Lines changed: 7 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -22,13 +22,11 @@ body: |
2222
; RV32I-MO-LABEL: name: func1
2323
; RV32I-MO: liveins: $x10, $x11
2424
; RV32I-MO-NEXT: {{ $}}
25-
; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
26-
; RV32I-MO-NEXT: PseudoRET
25+
; RV32I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
2726
; RV64I-MO-LABEL: name: func1
2827
; RV64I-MO: liveins: $x10, $x11
2928
; RV64I-MO-NEXT: {{ $}}
30-
; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
31-
; RV64I-MO-NEXT: PseudoRET
29+
; RV64I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
3230
$x10 = ORI $x10, 1023
3331
CFI_INSTRUCTION offset $x1, 0
3432
$x11 = ORI $x11, 1023
@@ -49,13 +47,11 @@ body: |
4947
; RV32I-MO-LABEL: name: func2
5048
; RV32I-MO: liveins: $x10, $x11
5149
; RV32I-MO-NEXT: {{ $}}
52-
; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
53-
; RV32I-MO-NEXT: PseudoRET
50+
; RV32I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
5451
; RV64I-MO-LABEL: name: func2
5552
; RV64I-MO: liveins: $x10, $x11
5653
; RV64I-MO-NEXT: {{ $}}
57-
; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
58-
; RV64I-MO-NEXT: PseudoRET
54+
; RV64I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
5955
$x10 = ORI $x10, 1023
6056
CFI_INSTRUCTION offset $x1, 0
6157
$x11 = ORI $x11, 1023
@@ -76,13 +72,11 @@ body: |
7672
; RV32I-MO-LABEL: name: func3
7773
; RV32I-MO: liveins: $x10, $x11
7874
; RV32I-MO-NEXT: {{ $}}
79-
; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
80-
; RV32I-MO-NEXT: PseudoRET
75+
; RV32I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
8176
; RV64I-MO-LABEL: name: func3
8277
; RV64I-MO: liveins: $x10, $x11
8378
; RV64I-MO-NEXT: {{ $}}
84-
; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
85-
; RV64I-MO-NEXT: PseudoRET
79+
; RV64I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
8680
$x10 = ORI $x10, 1023
8781
CFI_INSTRUCTION offset $x1, -12
8882
$x11 = ORI $x11, 1023
@@ -103,4 +97,4 @@ body: |
10397
# OUTLINED-NEXT: $x12 = ADDI $x10, 17
10498
# OUTLINED-NEXT: $x11 = AND $x12, $x11
10599
# OUTLINED-NEXT: $x10 = SUB $x10, $x11
106-
# OUTLINED-NEXT: $x0 = JALR $x5, 0
100+
# OUTLINED-NEXT: PseudoRET

‎llvm/test/CodeGen/RISCV/machine-outliner-leaf-descendants.ll‎

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -94,25 +94,28 @@ define i32 @_Z2f6v() minsize {
9494
; CHECK-BASELINE-NEXT: li a3, 0x4
9595
; CHECK-BASELINE-NEXT: li a4, 0x5
9696
; CHECK-BASELINE-NEXT: li a5, 0x6
97-
; CHECK-BASELINE-NEXT: jr t0
97+
; CHECK-BASELINE-NEXT: auipc t1, 0x0
98+
; CHECK-BASELINE-NEXT: jr t1 <OUTLINED_FUNCTION_0+0x18>
9899

99100
; CHECK-BASELINE: <OUTLINED_FUNCTION_1>:
100101
; CHECK-BASELINE-NEXT: li a0, 0x1
101102
; CHECK-BASELINE-NEXT: li a1, 0x2
102103
; CHECK-BASELINE-NEXT: li a2, 0x3
103104
; CHECK-BASELINE-NEXT: li a3, 0x4
104105
; CHECK-BASELINE-NEXT: li a4, 0x5
105-
; CHECK-BASELINE-NEXT: li a5, 0x7
106-
; CHECK-BASELINE-NEXT: jr t0
106+
; CHECK-BASELINE-NEXT: li a5, 0x8
107+
; CHECK-BASELINE-NEXT: auipc t1, 0x0
108+
; CHECK-BASELINE-NEXT: jr t1 <OUTLINED_FUNCTION_1+0x18>
107109

108110
; CHECK-BASELINE: <OUTLINED_FUNCTION_2>:
109111
; CHECK-BASELINE-NEXT: li a0, 0x1
110112
; CHECK-BASELINE-NEXT: li a1, 0x2
111113
; CHECK-BASELINE-NEXT: li a2, 0x3
112114
; CHECK-BASELINE-NEXT: li a3, 0x4
113115
; CHECK-BASELINE-NEXT: li a4, 0x5
114-
; CHECK-BASELINE-NEXT: li a5, 0x8
115-
; CHECK-BASELINE-NEXT: jr t0
116+
; CHECK-BASELINE-NEXT: li a5, 0x7
117+
; CHECK-BASELINE-NEXT: auipc t1, 0x0
118+
; CHECK-BASELINE-NEXT: jr t1 <OUTLINED_FUNCTION_2+0x18>
116119

117120
; CHECK-LEAF-DESCENDANTS: <OUTLINED_FUNCTION_0>:
118121
; CHECK-LEAF-DESCENDANTS-NEXT: li a0, 0x1

‎llvm/test/CodeGen/RISCV/machine-outliner-patchable.ll‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -10,8 +10,8 @@ define void @fentry0(i1 %a) nounwind "fentry-call"="true" {
1010
; CHECK-LABEL: fentry0:
1111
; CHECK-NEXT: # %bb.0:
1212
; CHECK-NEXT: # FEntry call
13-
; CHECK: # %bb.1:
14-
; CHECK-NEXT: call t0, OUTLINED_FUNCTION_1
13+
; CHECK: .LBB0_2:
14+
; CHECK-NEXT: tail OUTLINED_FUNCTION_0
1515
entry:
1616
br i1 %a, label %if.then, label %if.end
1717
if.then:
@@ -26,8 +26,8 @@ define void @fentry1(i1 %a) nounwind "fentry-call"="true" {
2626
; CHECK-LABEL: fentry1:
2727
; CHECK-NEXT: # %bb.0:
2828
; CHECK-NEXT: # FEntry call
29-
; CHECK: # %bb.1:
30-
; CHECK-NEXT: call t0, OUTLINED_FUNCTION_1
29+
; CHECK: .LBB1_2:
30+
; CHECK-NEXT: tail OUTLINED_FUNCTION_0
3131
entry:
3232
br i1 %a, label %if.then, label %if.end
3333
if.then:
@@ -46,8 +46,8 @@ define void @patchable0(i1 %a) nounwind "patchable-function-entry"="2" {
4646
; CHECK-NEXT: # %bb.0:
4747
; CHECK-NEXT: nop
4848
; CHECK-NEXT: nop
49-
; CHECK: # %bb.1:
50-
; CHECK-NEXT: call t0, OUTLINED_FUNCTION_1
49+
; CHECK: .LBB2_2:
50+
; CHECK-NEXT: tail OUTLINED_FUNCTION_0
5151
entry:
5252
br i1 %a, label %if.then, label %if.end
5353
if.then:
@@ -64,8 +64,8 @@ define void @patchable1(i1 %a) nounwind "patchable-function-entry"="2" {
6464
; CHECK-NEXT: # %bb.0:
6565
; CHECK-NEXT: nop
6666
; CHECK-NEXT: nop
67-
; CHECK: # %bb.1:
68-
; CHECK-NEXT: call t0, OUTLINED_FUNCTION_1
67+
; CHECK: .LBB3_2:
68+
; CHECK-NEXT: tail OUTLINED_FUNCTION_0
6969
entry:
7070
br i1 %a, label %if.then, label %if.end
7171
if.then:

‎llvm/test/CodeGen/RISCV/machine-outliner-position.mir‎

Lines changed: 6 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -25,15 +25,13 @@ body: |
2525
; RV32I-MO-NEXT: {{ $}}
2626
; RV32I-MO-NEXT: $x10 = ORI $x10, 1023
2727
; RV32I-MO-NEXT: EH_LABEL <mcsymbol .Ltmp0>
28-
; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
29-
; RV32I-MO-NEXT: PseudoRET
28+
; RV32I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
3029
; RV64I-MO-LABEL: name: func1
3130
; RV64I-MO: liveins: $x10, $x11
3231
; RV64I-MO-NEXT: {{ $}}
3332
; RV64I-MO-NEXT: $x10 = ORI $x10, 1023
3433
; RV64I-MO-NEXT: EH_LABEL <mcsymbol .Ltmp0>
35-
; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
36-
; RV64I-MO-NEXT: PseudoRET
34+
; RV64I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
3735
$x10 = ORI $x10, 1023
3836
EH_LABEL <mcsymbol .Ltmp0>
3937
$x11 = ORI $x11, 1023
@@ -53,15 +51,13 @@ body: |
5351
; RV32I-MO-NEXT: {{ $}}
5452
; RV32I-MO-NEXT: $x10 = ORI $x10, 1023
5553
; RV32I-MO-NEXT: GC_LABEL <mcsymbol .Ltmp1>
56-
; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
57-
; RV32I-MO-NEXT: PseudoRET
54+
; RV32I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
5855
; RV64I-MO-LABEL: name: func2
5956
; RV64I-MO: liveins: $x10, $x11
6057
; RV64I-MO-NEXT: {{ $}}
6158
; RV64I-MO-NEXT: $x10 = ORI $x10, 1023
6259
; RV64I-MO-NEXT: GC_LABEL <mcsymbol .Ltmp1>
63-
; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
64-
; RV64I-MO-NEXT: PseudoRET
60+
; RV64I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
6561
$x10 = ORI $x10, 1023
6662
GC_LABEL <mcsymbol .Ltmp1>
6763
$x11 = ORI $x11, 1023
@@ -81,15 +77,13 @@ body: |
8177
; RV32I-MO-NEXT: {{ $}}
8278
; RV32I-MO-NEXT: $x10 = ORI $x10, 1023
8379
; RV32I-MO-NEXT: ANNOTATION_LABEL <mcsymbol .Ltmp2>
84-
; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
85-
; RV32I-MO-NEXT: PseudoRET
80+
; RV32I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
8681
; RV64I-MO-LABEL: name: func3
8782
; RV64I-MO: liveins: $x10, $x11
8883
; RV64I-MO-NEXT: {{ $}}
8984
; RV64I-MO-NEXT: $x10 = ORI $x10, 1023
9085
; RV64I-MO-NEXT: ANNOTATION_LABEL <mcsymbol .Ltmp2>
91-
; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
92-
; RV64I-MO-NEXT: PseudoRET
86+
; RV64I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
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$x10 = ORI $x10, 1023
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ANNOTATION_LABEL <mcsymbol .Ltmp2>
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$x11 = ORI $x11, 1023

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