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davemgreendavemgreen
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[ARM] Add neon vector support for round
As per #142559, this marks fround as legal for Neon and upgrades the existing arm.neon.vrinta intrinsics.
1 parent a1d8331 commit 6bd9ff0

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8 files changed

+16
-60
lines changed

8 files changed

+16
-60
lines changed

‎clang/lib/CodeGen/TargetBuiltins/ARM.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -839,8 +839,8 @@ static const ARMVectorIntrinsicInfo ARMSIMDIntrinsicMap [] = {
839839
NEONMAP2(vrhadd_v, arm_neon_vrhaddu, arm_neon_vrhadds, Add1ArgType | UnsignedAlts),
840840
NEONMAP2(vrhaddq_v, arm_neon_vrhaddu, arm_neon_vrhadds, Add1ArgType | UnsignedAlts),
841841
NEONMAP1(vrnd_v, arm_neon_vrintz, Add1ArgType),
842-
NEONMAP1(vrnda_v, arm_neon_vrinta, Add1ArgType),
843-
NEONMAP1(vrndaq_v, arm_neon_vrinta, Add1ArgType),
842+
NEONMAP1(vrnda_v, round, Add1ArgType),
843+
NEONMAP1(vrndaq_v, round, Add1ArgType),
844844
NEONMAP0(vrndi_v),
845845
NEONMAP0(vrndiq_v),
846846
NEONMAP1(vrndm_v, floor, Add1ArgType),

‎clang/test/CodeGen/arm-neon-directed-rounding.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@
1616
// CHECK-A32-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
1717
// CHECK-A32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
1818
// CHECK-A32-NEXT: [[VRNDA_V_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
19-
// CHECK-A32-NEXT: [[VRNDA_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrinta.v2f32(<2 x float> [[VRNDA_V_I]])
19+
// CHECK-A32-NEXT: [[VRNDA_V1_I:%.*]] = call <2 x float> @llvm.round.v2f32(<2 x float> [[VRNDA_V_I]])
2020
// CHECK-A32-NEXT: [[VRNDA_V2_I:%.*]] = bitcast <2 x float> [[VRNDA_V1_I]] to <8 x i8>
2121
// CHECK-A32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VRNDA_V2_I]] to <2 x i32>
2222
// CHECK-A32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to <2 x float>
@@ -41,7 +41,7 @@ float32x2_t test_vrnda_f32(float32x2_t a) {
4141
// CHECK-A32-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
4242
// CHECK-A32-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
4343
// CHECK-A32-NEXT: [[VRNDAQ_V_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
44-
// CHECK-A32-NEXT: [[VRNDAQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrinta.v4f32(<4 x float> [[VRNDAQ_V_I]])
44+
// CHECK-A32-NEXT: [[VRNDAQ_V1_I:%.*]] = call <4 x float> @llvm.round.v4f32(<4 x float> [[VRNDAQ_V_I]])
4545
// CHECK-A32-NEXT: [[VRNDAQ_V2_I:%.*]] = bitcast <4 x float> [[VRNDAQ_V1_I]] to <16 x i8>
4646
// CHECK-A32-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VRNDAQ_V2_I]] to <4 x i32>
4747
// CHECK-A32-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP2]] to <4 x float>

‎clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -554,7 +554,7 @@ float16x8_t test_vrndq_f16(float16x8_t a) {
554554
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <4 x i16>
555555
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>
556556
// CHECK-NEXT: [[VRNDA_V_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half>
557-
// CHECK-NEXT: [[VRNDA_V1_I:%.*]] = call <4 x half> @llvm.arm.neon.vrinta.v4f16(<4 x half> [[VRNDA_V_I]])
557+
// CHECK-NEXT: [[VRNDA_V1_I:%.*]] = call <4 x half> @llvm.round.v4f16(<4 x half> [[VRNDA_V_I]])
558558
// CHECK-NEXT: [[VRNDA_V2_I:%.*]] = bitcast <4 x half> [[VRNDA_V1_I]] to <8 x i8>
559559
// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VRNDA_V2_I]] to <4 x i16>
560560
// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to <4 x half>
@@ -570,7 +570,7 @@ float16x4_t test_vrnda_f16(float16x4_t a) {
570570
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <8 x i16>
571571
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>
572572
// CHECK-NEXT: [[VRNDAQ_V_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>
573-
// CHECK-NEXT: [[VRNDAQ_V1_I:%.*]] = call <8 x half> @llvm.arm.neon.vrinta.v8f16(<8 x half> [[VRNDAQ_V_I]])
573+
// CHECK-NEXT: [[VRNDAQ_V1_I:%.*]] = call <8 x half> @llvm.round.v8f16(<8 x half> [[VRNDAQ_V_I]])
574574
// CHECK-NEXT: [[VRNDAQ_V2_I:%.*]] = bitcast <8 x half> [[VRNDAQ_V1_I]] to <16 x i8>
575575
// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VRNDAQ_V2_I]] to <8 x i16>
576576
// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP2]] to <8 x half>

‎llvm/include/llvm/IR/IntrinsicsARM.td‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -680,7 +680,6 @@ def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
680680
// Vector and Scalar Rounding.
681681
def int_arm_neon_vrintn : Neon_1FloatArg_Intrinsic;
682682
def int_arm_neon_vrintx : Neon_1Arg_Intrinsic;
683-
def int_arm_neon_vrinta : Neon_1Arg_Intrinsic;
684683
def int_arm_neon_vrintz : Neon_1Arg_Intrinsic;
685684
def int_arm_neon_vrintp : Neon_1Arg_Intrinsic;
686685

‎llvm/lib/IR/AutoUpgrade.cpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -720,6 +720,7 @@ static bool upgradeArmOrAarch64IntrinsicFunction(bool IsArm, Function *F,
720720
.StartsWith("vqsubs.", Intrinsic::ssub_sat)
721721
.StartsWith("vqsubu.", Intrinsic::usub_sat)
722722
.StartsWith("vrintm.", Intrinsic::floor)
723+
.StartsWith("vrinta.", Intrinsic::round)
723724
.Default(Intrinsic::not_intrinsic);
724725
if (ID != Intrinsic::not_intrinsic) {
725726
NewFn = Intrinsic::getOrInsertDeclaration(F->getParent(), ID,

‎llvm/lib/Target/ARM/ARMISelLowering.cpp‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1546,6 +1546,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM_,
15461546
if (Subtarget->hasV8Ops()) {
15471547
setOperationAction(ISD::FFLOOR, MVT::v2f32, Legal);
15481548
setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1549+
setOperationAction(ISD::FROUND, MVT::v2f32, Legal);
1550+
setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
15491551
}
15501552

15511553
if (Subtarget->hasFullFP16()) {
@@ -1561,6 +1563,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM_,
15611563

15621564
setOperationAction(ISD::FFLOOR, MVT::v4f16, Legal);
15631565
setOperationAction(ISD::FFLOOR, MVT::v8f16, Legal);
1566+
setOperationAction(ISD::FROUND, MVT::v4f16, Legal);
1567+
setOperationAction(ISD::FROUND, MVT::v8f16, Legal);
15641568
}
15651569
}
15661570

‎llvm/lib/Target/ARM/ARMInstrNEON.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7314,7 +7314,7 @@ multiclass VRINT_FPI<string op, bits<3> op9_7, SDPatternOperator Int> {
73147314

73157315
defm VRINTNN : VRINT_FPI<"n", 0b000, int_arm_neon_vrintn>;
73167316
defm VRINTXN : VRINT_FPI<"x", 0b001, int_arm_neon_vrintx>;
7317-
defm VRINTAN : VRINT_FPI<"a", 0b010, int_arm_neon_vrinta>;
7317+
defm VRINTAN : VRINT_FPI<"a", 0b010, fround>;
73187318
defm VRINTZN : VRINT_FPI<"z", 0b011, int_arm_neon_vrintz>;
73197319
defm VRINTMN : VRINT_FPI<"m", 0b101, ffloor>;
73207320
defm VRINTPN : VRINT_FPI<"p", 0b111, int_arm_neon_vrintp>;

‎llvm/test/CodeGen/ARM/vrint.ll‎

Lines changed: 4 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -79,21 +79,7 @@ define <4 x half> @frinta_4h(<4 x half> %A) nounwind {
7979
;
8080
; CHECK-FP16-LABEL: frinta_4h:
8181
; CHECK-FP16: @ %bb.0:
82-
; CHECK-FP16-NEXT: vmovx.f16 s2, s0
83-
; CHECK-FP16-NEXT: vrinta.f16 s2, s2
84-
; CHECK-FP16-NEXT: vmov r0, s2
85-
; CHECK-FP16-NEXT: vrinta.f16 s2, s0
86-
; CHECK-FP16-NEXT: vmov r1, s2
87-
; CHECK-FP16-NEXT: vrinta.f16 s2, s1
88-
; CHECK-FP16-NEXT: vmovx.f16 s0, s1
89-
; CHECK-FP16-NEXT: vrinta.f16 s0, s0
90-
; CHECK-FP16-NEXT: vmov.16 d16[0], r1
91-
; CHECK-FP16-NEXT: vmov.16 d16[1], r0
92-
; CHECK-FP16-NEXT: vmov r0, s2
93-
; CHECK-FP16-NEXT: vmov.16 d16[2], r0
94-
; CHECK-FP16-NEXT: vmov r0, s0
95-
; CHECK-FP16-NEXT: vmov.16 d16[3], r0
96-
; CHECK-FP16-NEXT: vorr d0, d16, d16
82+
; CHECK-FP16-NEXT: vrinta.f16 d0, d0
9783
; CHECK-FP16-NEXT: bx lr
9884
%tmp3 = call <4 x half> @llvm.round.v4f16(<4 x half> %A)
9985
ret <4 x half> %tmp3
@@ -243,35 +229,7 @@ define <8 x half> @frinta_8h(<8 x half> %A) nounwind {
243229
;
244230
; CHECK-FP16-LABEL: frinta_8h:
245231
; CHECK-FP16: @ %bb.0:
246-
; CHECK-FP16-NEXT: vmovx.f16 s4, s2
247-
; CHECK-FP16-NEXT: vrinta.f16 s4, s4
248-
; CHECK-FP16-NEXT: vmov r0, s4
249-
; CHECK-FP16-NEXT: vrinta.f16 s4, s2
250-
; CHECK-FP16-NEXT: vmov r1, s4
251-
; CHECK-FP16-NEXT: vrinta.f16 s4, s3
252-
; CHECK-FP16-NEXT: vmov.16 d17[0], r1
253-
; CHECK-FP16-NEXT: vmov.16 d17[1], r0
254-
; CHECK-FP16-NEXT: vmov r0, s4
255-
; CHECK-FP16-NEXT: vmovx.f16 s4, s3
256-
; CHECK-FP16-NEXT: vrinta.f16 s4, s4
257-
; CHECK-FP16-NEXT: vmov.16 d17[2], r0
258-
; CHECK-FP16-NEXT: vmov r0, s4
259-
; CHECK-FP16-NEXT: vmovx.f16 s4, s0
260-
; CHECK-FP16-NEXT: vrinta.f16 s4, s4
261-
; CHECK-FP16-NEXT: vmov.16 d17[3], r0
262-
; CHECK-FP16-NEXT: vmov r0, s4
263-
; CHECK-FP16-NEXT: vrinta.f16 s4, s0
264-
; CHECK-FP16-NEXT: vmovx.f16 s0, s1
265-
; CHECK-FP16-NEXT: vmov r1, s4
266-
; CHECK-FP16-NEXT: vrinta.f16 s4, s1
267-
; CHECK-FP16-NEXT: vrinta.f16 s0, s0
268-
; CHECK-FP16-NEXT: vmov.16 d16[0], r1
269-
; CHECK-FP16-NEXT: vmov.16 d16[1], r0
270-
; CHECK-FP16-NEXT: vmov r0, s4
271-
; CHECK-FP16-NEXT: vmov.16 d16[2], r0
272-
; CHECK-FP16-NEXT: vmov r0, s0
273-
; CHECK-FP16-NEXT: vmov.16 d16[3], r0
274-
; CHECK-FP16-NEXT: vorr q0, q8, q8
232+
; CHECK-FP16-NEXT: vrinta.f16 q0, q0
275233
; CHECK-FP16-NEXT: bx lr
276234
%tmp3 = call <8 x half> @llvm.round.v8f16(<8 x half> %A)
277235
ret <8 x half> %tmp3
@@ -297,9 +255,7 @@ define <2 x float> @frinta_2s(<2 x float> %A) nounwind {
297255
;
298256
; CHECK-LABEL: frinta_2s:
299257
; CHECK: @ %bb.0:
300-
; CHECK-NEXT: vrinta.f32 s3, s1
301-
; CHECK-NEXT: vrinta.f32 s2, s0
302-
; CHECK-NEXT: vmov.f64 d0, d1
258+
; CHECK-NEXT: vrinta.f32 d0, d0
303259
; CHECK-NEXT: bx lr
304260
%tmp3 = call <2 x float> @llvm.round.v2f32(<2 x float> %A)
305261
ret <2 x float> %tmp3
@@ -331,11 +287,7 @@ define <4 x float> @frinta_4s(<4 x float> %A) nounwind {
331287
;
332288
; CHECK-LABEL: frinta_4s:
333289
; CHECK: @ %bb.0:
334-
; CHECK-NEXT: vrinta.f32 s7, s3
335-
; CHECK-NEXT: vrinta.f32 s6, s2
336-
; CHECK-NEXT: vrinta.f32 s5, s1
337-
; CHECK-NEXT: vrinta.f32 s4, s0
338-
; CHECK-NEXT: vorr q0, q1, q1
290+
; CHECK-NEXT: vrinta.f32 q0, q0
339291
; CHECK-NEXT: bx lr
340292
%tmp3 = call <4 x float> @llvm.round.v4f32(<4 x float> %A)
341293
ret <4 x float> %tmp3

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