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author
Thorsten Schütt
committed
update combine set
1 parent d201def commit 6bf97b2

17 files changed

+358
-396
lines changed

‎llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp‎

Lines changed: 35 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -412,41 +412,41 @@ bool CombinerHelper::matchCombineZextTrunc(const MachineInstr &ZextMI,
412412
return true;
413413
}
414414

415-
if (SrcSize < DstSize) {
416-
// zext(Src & mask).
417-
418-
if (!isLegalOrBeforeLegalizer({TargetOpcode::G_AND, {SrcTy}}) ||
419-
!isConstantLegalOrBeforeLegalizer(SrcTy) ||
420-
!isLegalOrBeforeLegalizer({TargetOpcode::G_ZEXT, {DstTy, SrcTy}}))
421-
return false;
422-
423-
APInt AndValue(APInt::getLowBitsSet(SrcSize, MidSize));
424-
425-
MatchInfo = [=](MachineIRBuilder &B) {
426-
auto Mask = B.buildConstant(SrcTy, AndValue);
427-
auto And = B.buildAnd(SrcTy, Src, Mask);
428-
B.buildZExt(Dst, And);
429-
};
430-
return true;
431-
}
432-
433-
if (SrcSize > DstSize) {
434-
// trunc(Src) & mask.
435-
436-
if (!isLegalOrBeforeLegalizer({TargetOpcode::G_AND, {DstTy}}) ||
437-
!isConstantLegalOrBeforeLegalizer(DstTy) ||
438-
!isLegalOrBeforeLegalizer({TargetOpcode::G_TRUNC, {DstTy, SrcTy}}))
439-
return false;
440-
441-
APInt AndValue(APInt::getLowBitsSet(DstSize, MidSize));
442-
443-
MatchInfo = [=](MachineIRBuilder &B) {
444-
auto Mask = B.buildConstant(DstTy, AndValue);
445-
auto Trunc = B.buildTrunc(DstTy, Src);
446-
B.buildAnd(Dst, Trunc, Mask);
447-
};
448-
return true;
449-
}
415+
// if (SrcSize < DstSize) {
416+
// // zext(Src & mask).
417+
//
418+
// if (!isLegalOrBeforeLegalizer({TargetOpcode::G_AND, {SrcTy}}) ||
419+
// !isConstantLegalOrBeforeLegalizer(SrcTy) ||
420+
// !isLegalOrBeforeLegalizer({TargetOpcode::G_ZEXT, {DstTy, SrcTy}}))
421+
// return false;
422+
//
423+
// APInt AndValue(APInt::getLowBitsSet(SrcSize, MidSize));
424+
//
425+
// MatchInfo = [=](MachineIRBuilder &B) {
426+
// auto Mask = B.buildConstant(SrcTy, AndValue);
427+
// auto And = B.buildAnd(SrcTy, Src, Mask);
428+
// B.buildZExt(Dst, And);
429+
// };
430+
// return true;
431+
// }
432+
433+
// if (SrcSize > DstSize) {
434+
// // trunc(Src) & mask.
435+
//
436+
// if (!isLegalOrBeforeLegalizer({TargetOpcode::G_AND, {DstTy}}) ||
437+
// !isConstantLegalOrBeforeLegalizer(DstTy) ||
438+
// !isLegalOrBeforeLegalizer({TargetOpcode::G_TRUNC, {DstTy, SrcTy}}))
439+
// return false;
440+
//
441+
// APInt AndValue(APInt::getLowBitsSet(DstSize, MidSize));
442+
//
443+
// MatchInfo = [=](MachineIRBuilder &B) {
444+
// auto Mask = B.buildConstant(DstTy, AndValue);
445+
// auto Trunc = B.buildTrunc(DstTy, Src);
446+
// B.buildAnd(Dst, Trunc, Mask);
447+
// };
448+
// return true;
449+
// }
450450

451451
return false;
452452
}

‎llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll‎

Lines changed: 10 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1938,14 +1938,14 @@ define i8 @atomicrmw_add_i8(ptr %ptr, i8 %rhs) {
19381938
define i8 @atomicrmw_xchg_i8(ptr %ptr, i8 %rhs) {
19391939
; CHECK-NOLSE-O1-LABEL: atomicrmw_xchg_i8:
19401940
; CHECK-NOLSE-O1: ; %bb.0:
1941-
; CHECK-NOLSE-O1-NEXT: mov x8, x0
1941+
; CHECK-NOLSE-O1-NEXT: ; kill: def $w1 killed $w1 def $x1
19421942
; CHECK-NOLSE-O1-NEXT: LBB28_1: ; %atomicrmw.start
19431943
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
1944-
; CHECK-NOLSE-O1-NEXT: ldxrb w0, [x8]
1945-
; CHECK-NOLSE-O1-NEXT: stxrb w9, w1, [x8]
1944+
; CHECK-NOLSE-O1-NEXT: ldxrb w8, [x0]
1945+
; CHECK-NOLSE-O1-NEXT: stxrb w9, w1, [x0]
19461946
; CHECK-NOLSE-O1-NEXT: cbnz w9, LBB28_1
19471947
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
1948-
; CHECK-NOLSE-O1-NEXT: ; kill: def $w0 killed $w0 killed $x0
1948+
; CHECK-NOLSE-O1-NEXT: mov w0, w8
19491949
; CHECK-NOLSE-O1-NEXT: ret
19501950
;
19511951
; CHECK-OUTLINE-O1-LABEL: atomicrmw_xchg_i8:
@@ -2993,14 +2993,14 @@ define i16 @atomicrmw_add_i16(ptr %ptr, i16 %rhs) {
29932993
define i16 @atomicrmw_xchg_i16(ptr %ptr, i16 %rhs) {
29942994
; CHECK-NOLSE-O1-LABEL: atomicrmw_xchg_i16:
29952995
; CHECK-NOLSE-O1: ; %bb.0:
2996-
; CHECK-NOLSE-O1-NEXT: mov x8, x0
2996+
; CHECK-NOLSE-O1-NEXT: ; kill: def $w1 killed $w1 def $x1
29972997
; CHECK-NOLSE-O1-NEXT: LBB38_1: ; %atomicrmw.start
29982998
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
2999-
; CHECK-NOLSE-O1-NEXT: ldxrh w0, [x8]
3000-
; CHECK-NOLSE-O1-NEXT: stxrh w9, w1, [x8]
2999+
; CHECK-NOLSE-O1-NEXT: ldxrh w8, [x0]
3000+
; CHECK-NOLSE-O1-NEXT: stxrh w9, w1, [x0]
30013001
; CHECK-NOLSE-O1-NEXT: cbnz w9, LBB38_1
30023002
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
3003-
; CHECK-NOLSE-O1-NEXT: ; kill: def $w0 killed $w0 killed $x0
3003+
; CHECK-NOLSE-O1-NEXT: mov w0, w8
30043004
; CHECK-NOLSE-O1-NEXT: ret
30053005
;
30063006
; CHECK-OUTLINE-O1-LABEL: atomicrmw_xchg_i16:
@@ -5996,6 +5996,7 @@ define { i8, i1 } @cmpxchg_i8(ptr %ptr, i8 %desired, i8 %new) {
59965996
; CHECK-NOLSE-O1-LABEL: cmpxchg_i8:
59975997
; CHECK-NOLSE-O1: ; %bb.0:
59985998
; CHECK-NOLSE-O1-NEXT: mov x8, x0
5999+
; CHECK-NOLSE-O1-NEXT: ; kill: def $w2 killed $w2 def $x2
59996000
; CHECK-NOLSE-O1-NEXT: LBB67_1: ; %cmpxchg.start
60006001
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
60016002
; CHECK-NOLSE-O1-NEXT: ldxrb w0, [x8]
@@ -6102,6 +6103,7 @@ define { i16, i1 } @cmpxchg_i16(ptr %ptr, i16 %desired, i16 %new) {
61026103
; CHECK-NOLSE-O1-LABEL: cmpxchg_i16:
61036104
; CHECK-NOLSE-O1: ; %bb.0:
61046105
; CHECK-NOLSE-O1-NEXT: mov x8, x0
6106+
; CHECK-NOLSE-O1-NEXT: ; kill: def $w2 killed $w2 def $x2
61056107
; CHECK-NOLSE-O1-NEXT: LBB68_1: ; %cmpxchg.start
61066108
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
61076109
; CHECK-NOLSE-O1-NEXT: ldxrh w0, [x8]

‎llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll‎

Lines changed: 18 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -746,20 +746,20 @@ define i8 @atomicrmw_xchg_i8(ptr %ptr, i8 %rhs) {
746746
; CHECK-NEXT: successors: %bb.1(0x80000000)
747747
; CHECK-NEXT: liveins: $w1, $x0
748748
; CHECK-NEXT: {{ $}}
749-
; CHECK-NEXT: $x8 = ORRXrs $xzr, $x0, 0
749+
; CHECK-NEXT: renamable $w1 = KILL $w1, implicit-def $x1
750750
; CHECK-NEXT: {{ $}}
751751
; CHECK-NEXT: bb.1.atomicrmw.start:
752752
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
753-
; CHECK-NEXT: liveins: $w1, $x8
753+
; CHECK-NEXT: liveins: $x0, $x1
754754
; CHECK-NEXT: {{ $}}
755-
; CHECK-NEXT: renamable $w0 = LDXRB renamable $x8, implicit-def $x0, pcsections !0 :: (volatile load (s8) from %ir.ptr)
756-
; CHECK-NEXT: early-clobber renamable $w9 = STXRB renamable $w1, renamable $x8, pcsections !0 :: (volatile store (s8) into %ir.ptr)
755+
; CHECK-NEXT: renamable $w8 = LDXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s8) from %ir.ptr)
756+
; CHECK-NEXT: early-clobber renamable $w9 = STXRB renamable $w1, renamable $x0, pcsections !0 :: (volatile store (s8) into %ir.ptr)
757757
; CHECK-NEXT: CBNZW killed renamable $w9, %bb.1, pcsections !0
758758
; CHECK-NEXT: {{ $}}
759759
; CHECK-NEXT: bb.2.atomicrmw.end:
760-
; CHECK-NEXT: liveins: $x0
760+
; CHECK-NEXT: liveins: $x8
761761
; CHECK-NEXT: {{ $}}
762-
; CHECK-NEXT: $w0 = KILL renamable $w0, implicit killed $x0
762+
; CHECK-NEXT: $w0 = ORRWrs $wzr, $w8, 0, implicit killed $x8
763763
; CHECK-NEXT: RET undef $lr, implicit $w0
764764
%res = atomicrmw xchg ptr %ptr, i8 %rhs monotonic, !pcsections !0
765765
ret i8 %res
@@ -999,20 +999,20 @@ define i16 @atomicrmw_xchg_i16(ptr %ptr, i16 %rhs) {
999999
; CHECK-NEXT: successors: %bb.1(0x80000000)
10001000
; CHECK-NEXT: liveins: $w1, $x0
10011001
; CHECK-NEXT: {{ $}}
1002-
; CHECK-NEXT: $x8 = ORRXrs $xzr, $x0, 0
1002+
; CHECK-NEXT: renamable $w1 = KILL $w1, implicit-def $x1
10031003
; CHECK-NEXT: {{ $}}
10041004
; CHECK-NEXT: bb.1.atomicrmw.start:
10051005
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
1006-
; CHECK-NEXT: liveins: $w1, $x8
1006+
; CHECK-NEXT: liveins: $x0, $x1
10071007
; CHECK-NEXT: {{ $}}
1008-
; CHECK-NEXT: renamable $w0 = LDXRH renamable $x8, implicit-def $x0, pcsections !0 :: (volatile load (s16) from %ir.ptr)
1009-
; CHECK-NEXT: early-clobber renamable $w9 = STXRH renamable $w1, renamable $x8, pcsections !0 :: (volatile store (s16) into %ir.ptr)
1008+
; CHECK-NEXT: renamable $w8 = LDXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s16) from %ir.ptr)
1009+
; CHECK-NEXT: early-clobber renamable $w9 = STXRH renamable $w1, renamable $x0, pcsections !0 :: (volatile store (s16) into %ir.ptr)
10101010
; CHECK-NEXT: CBNZW killed renamable $w9, %bb.1, pcsections !0
10111011
; CHECK-NEXT: {{ $}}
10121012
; CHECK-NEXT: bb.2.atomicrmw.end:
1013-
; CHECK-NEXT: liveins: $x0
1013+
; CHECK-NEXT: liveins: $x8
10141014
; CHECK-NEXT: {{ $}}
1015-
; CHECK-NEXT: $w0 = KILL renamable $w0, implicit killed $x0
1015+
; CHECK-NEXT: $w0 = ORRWrs $wzr, $w8, 0, implicit killed $x8
10161016
; CHECK-NEXT: RET undef $lr, implicit $w0
10171017
%res = atomicrmw xchg ptr %ptr, i16 %rhs monotonic, !pcsections !0
10181018
ret i16 %res
@@ -1229,10 +1229,11 @@ define { i8, i1 } @cmpxchg_i8(ptr %ptr, i8 %desired, i8 %new) {
12291229
; CHECK-NEXT: liveins: $w1, $w2, $x0
12301230
; CHECK-NEXT: {{ $}}
12311231
; CHECK-NEXT: $x8 = ORRXrs $xzr, $x0, 0
1232+
; CHECK-NEXT: renamable $w2 = KILL $w2, implicit-def $x2
12321233
; CHECK-NEXT: {{ $}}
12331234
; CHECK-NEXT: bb.1.cmpxchg.start:
12341235
; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.4(0x04000000)
1235-
; CHECK-NEXT: liveins: $w1, $w2, $x8
1236+
; CHECK-NEXT: liveins: $w1, $x2, $x8
12361237
; CHECK-NEXT: {{ $}}
12371238
; CHECK-NEXT: renamable $w0 = LDXRB renamable $x8, implicit-def $x0, pcsections !0 :: (volatile load (s8) from %ir.ptr)
12381239
; CHECK-NEXT: renamable $w9 = ANDWri renamable $w0, 7, pcsections !0
@@ -1241,7 +1242,7 @@ define { i8, i1 } @cmpxchg_i8(ptr %ptr, i8 %desired, i8 %new) {
12411242
; CHECK-NEXT: {{ $}}
12421243
; CHECK-NEXT: bb.2.cmpxchg.trystore:
12431244
; CHECK-NEXT: successors: %bb.3(0x04000000), %bb.1(0x7c000000)
1244-
; CHECK-NEXT: liveins: $w1, $w2, $x0, $x8
1245+
; CHECK-NEXT: liveins: $w1, $x0, $x2, $x8
12451246
; CHECK-NEXT: {{ $}}
12461247
; CHECK-NEXT: early-clobber renamable $w9 = STXRB renamable $w2, renamable $x8, pcsections !0 :: (volatile store (s8) into %ir.ptr)
12471248
; CHECK-NEXT: CBNZW killed renamable $w9, %bb.1
@@ -1271,10 +1272,11 @@ define { i16, i1 } @cmpxchg_i16(ptr %ptr, i16 %desired, i16 %new) {
12711272
; CHECK-NEXT: liveins: $w1, $w2, $x0
12721273
; CHECK-NEXT: {{ $}}
12731274
; CHECK-NEXT: $x8 = ORRXrs $xzr, $x0, 0
1275+
; CHECK-NEXT: renamable $w2 = KILL $w2, implicit-def $x2
12741276
; CHECK-NEXT: {{ $}}
12751277
; CHECK-NEXT: bb.1.cmpxchg.start:
12761278
; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.4(0x04000000)
1277-
; CHECK-NEXT: liveins: $w1, $w2, $x8
1279+
; CHECK-NEXT: liveins: $w1, $x2, $x8
12781280
; CHECK-NEXT: {{ $}}
12791281
; CHECK-NEXT: renamable $w0 = LDXRH renamable $x8, implicit-def $x0, pcsections !0 :: (volatile load (s16) from %ir.ptr)
12801282
; CHECK-NEXT: renamable $w9 = ANDWri renamable $w0, 15, pcsections !0
@@ -1283,7 +1285,7 @@ define { i16, i1 } @cmpxchg_i16(ptr %ptr, i16 %desired, i16 %new) {
12831285
; CHECK-NEXT: {{ $}}
12841286
; CHECK-NEXT: bb.2.cmpxchg.trystore:
12851287
; CHECK-NEXT: successors: %bb.3(0x04000000), %bb.1(0x7c000000)
1286-
; CHECK-NEXT: liveins: $w1, $w2, $x0, $x8
1288+
; CHECK-NEXT: liveins: $w1, $x0, $x2, $x8
12871289
; CHECK-NEXT: {{ $}}
12881290
; CHECK-NEXT: early-clobber renamable $w9 = STXRH renamable $w2, renamable $x8, pcsections !0 :: (volatile store (s16) into %ir.ptr)
12891291
; CHECK-NEXT: CBNZW killed renamable $w9, %bb.1

‎llvm/test/CodeGen/AArch64/GlobalISel/combine-select.mir‎

Lines changed: 7 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -361,11 +361,10 @@ body: |
361361
; CHECK: liveins: $x0, $x1, $x2
362362
; CHECK-NEXT: {{ $}}
363363
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
364+
; CHECK-NEXT: %c:_(s1) = G_TRUNC [[COPY]](s64)
364365
; CHECK-NEXT: %one:_(s8) = G_CONSTANT i8 101
365-
; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
366-
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64)
367-
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[C]]
368-
; CHECK-NEXT: %sel:_(s8) = G_ADD [[AND]], %one
366+
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT %c(s1)
367+
; CHECK-NEXT: %sel:_(s8) = G_ADD [[ZEXT]], %one
369368
; CHECK-NEXT: %ext:_(s32) = G_ANYEXT %sel(s8)
370369
; CHECK-NEXT: $w0 = COPY %ext(s32)
371370
%0:_(s64) = COPY $x0
@@ -418,11 +417,10 @@ body: |
418417
; CHECK: liveins: $x0, $x1, $x2
419418
; CHECK-NEXT: {{ $}}
420419
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
421-
; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
422-
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64)
423-
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[C]]
424-
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s8) = G_CONSTANT i8 6
425-
; CHECK-NEXT: %sel:_(s8) = G_SHL [[AND]], [[C1]](s8)
420+
; CHECK-NEXT: %c:_(s1) = G_TRUNC [[COPY]](s64)
421+
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT %c(s1)
422+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 6
423+
; CHECK-NEXT: %sel:_(s8) = G_SHL [[ZEXT]], [[C]](s8)
426424
; CHECK-NEXT: %ext:_(s32) = G_ANYEXT %sel(s8)
427425
; CHECK-NEXT: $w0 = COPY %ext(s32)
428426
%0:_(s64) = COPY $x0

‎llvm/test/CodeGen/AArch64/GlobalISel/combine-with-flags.mir‎

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -322,10 +322,8 @@ body: |
322322
; CHECK: liveins: $w0, $w1
323323
; CHECK-NEXT: {{ $}}
324324
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
325-
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
326-
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
327-
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[AND]](s32)
328-
; CHECK-NEXT: $x1 = COPY [[ZEXT]](s64)
325+
; CHECK-NEXT: %2:_(s64) = nneg G_ZEXT [[COPY]](s32)
326+
; CHECK-NEXT: $x1 = COPY %2(s64)
329327
%0:_(s32) = COPY $w0
330328
%2:_(s16) = nuw G_TRUNC %0
331329
%3:_(s64) = G_ZEXT %2
@@ -340,10 +338,8 @@ body: |
340338
; CHECK: liveins: $w0, $w1
341339
; CHECK-NEXT: {{ $}}
342340
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
343-
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
344-
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
345-
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
346-
; CHECK-NEXT: $w1 = COPY [[AND]](s32)
341+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = nuw G_TRUNC [[COPY]](s64)
342+
; CHECK-NEXT: $w1 = COPY [[TRUNC]](s32)
347343
%0:_(s64) = COPY $x0
348344
%2:_(s16) = nuw G_TRUNC %0
349345
%3:_(s32) = G_ZEXT %2

‎llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir‎

Lines changed: 22 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -94,14 +94,13 @@ body: |
9494
; CHECK-NEXT: {{ $}}
9595
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
9696
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
97-
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
98-
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
99-
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[AND]](s32)
100-
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 72340172838076673
101-
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C1]]
97+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
98+
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s8)
99+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 72340172838076673
100+
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]
102101
; CHECK-NEXT: G_STORE [[MUL]](s64), [[COPY]](p0) :: (store (s64) into %ir.dst, align 1)
103-
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
104-
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
102+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
103+
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](s64)
105104
; CHECK-NEXT: G_STORE [[MUL]](s64), [[PTR_ADD]](p0) :: (store (s64) into %ir.dst + 8, align 1)
106105
; CHECK-NEXT: RET_ReallyLR
107106
%0:_(p0) = COPY $x0
@@ -184,21 +183,20 @@ body: |
184183
; CHECK-NEXT: {{ $}}
185184
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
186185
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
187-
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
188-
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
189-
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[AND]](s32)
190-
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 72340172838076673
191-
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C1]]
186+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
187+
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s8)
188+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 72340172838076673
189+
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]
192190
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MUL]](s64), [[MUL]](s64)
193191
; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>) into %ir.dst, align 1)
194-
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
195-
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
192+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
193+
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](s64)
196194
; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into %ir.dst + 16, align 1)
197-
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
198-
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C3]](s64)
195+
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
196+
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
199197
; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[PTR_ADD1]](p0) :: (store (<2 x s64>) into %ir.dst + 32, align 1)
200-
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
201-
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C4]](s64)
198+
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
199+
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C3]](s64)
202200
; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[PTR_ADD2]](p0) :: (store (<2 x s64>) into %ir.dst + 44, align 1)
203201
; CHECK-NEXT: RET_ReallyLR
204202
%0:_(p0) = COPY $x0
@@ -250,14 +248,13 @@ body: |
250248
; CHECK-NEXT: {{ $}}
251249
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
252250
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
253-
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
254-
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
255-
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[AND]](s32)
256-
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 72340172838076673
257-
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C1]]
251+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
252+
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s8)
253+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 72340172838076673
254+
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]
258255
; CHECK-NEXT: G_STORE [[MUL]](s64), [[COPY]](p0) :: (store (s64) into %ir.dst, align 1)
259-
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
260-
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
256+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
257+
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](s64)
261258
; CHECK-NEXT: G_STORE [[MUL]](s64), [[PTR_ADD]](p0) :: (store (s64) into %ir.dst + 8, align 1)
262259
; CHECK-NEXT: RET_ReallyLR
263260
%0:_(p0) = COPY $x0

‎llvm/test/CodeGen/AArch64/aarch64-mops.ll‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -432,8 +432,9 @@ define void @memset_10(ptr %dst, i32 %value) {
432432
;
433433
; GISel-WITHOUT-MOPS-O3-LABEL: memset_10:
434434
; GISel-WITHOUT-MOPS-O3: // %bb.0: // %entry
435+
; GISel-WITHOUT-MOPS-O3-NEXT: // kill: def $w1 killed $w1 def $x1
435436
; GISel-WITHOUT-MOPS-O3-NEXT: mov x8, #72340172838076673 // =0x101010101010101
436-
; GISel-WITHOUT-MOPS-O3-NEXT: and w9, w1, #0xff
437+
; GISel-WITHOUT-MOPS-O3-NEXT: and x9, x1, #0xff
437438
; GISel-WITHOUT-MOPS-O3-NEXT: mul x8, x9, x8
438439
; GISel-WITHOUT-MOPS-O3-NEXT: str x8, [x0]
439440
; GISel-WITHOUT-MOPS-O3-NEXT: strh w8, [x0, #8]
@@ -453,8 +454,9 @@ define void @memset_10(ptr %dst, i32 %value) {
453454
;
454455
; GISel-MOPS-O3-LABEL: memset_10:
455456
; GISel-MOPS-O3: // %bb.0: // %entry
457+
; GISel-MOPS-O3-NEXT: // kill: def $w1 killed $w1 def $x1
456458
; GISel-MOPS-O3-NEXT: mov x8, #72340172838076673 // =0x101010101010101
457-
; GISel-MOPS-O3-NEXT: and w9, w1, #0xff
459+
; GISel-MOPS-O3-NEXT: and x9, x1, #0xff
458460
; GISel-MOPS-O3-NEXT: mul x8, x9, x8
459461
; GISel-MOPS-O3-NEXT: str x8, [x0]
460462
; GISel-MOPS-O3-NEXT: strh w8, [x0, #8]

‎llvm/test/CodeGen/AArch64/aarch64-smull.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1750,11 +1750,11 @@ define <8 x i16> @umull_smaller_v8i16(<8 x i4> %src1, <8 x i16> %src2) {
17501750
;
17511751
; CHECK-GI-LABEL: umull_smaller_v8i16:
17521752
; CHECK-GI: // %bb.0: // %entry
1753-
; CHECK-GI-NEXT: movi v2.8b, #15
1754-
; CHECK-GI-NEXT: movi v3.2d, #0xff00ff00ff00ff
1755-
; CHECK-GI-NEXT: and v0.8b, v0.8b, v2.8b
1756-
; CHECK-GI-NEXT: and v1.16b, v1.16b, v3.16b
1753+
; CHECK-GI-NEXT: movi v2.2d, #0xff00ff00ff00ff
1754+
; CHECK-GI-NEXT: movi v3.8h, #15
17571755
; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
1756+
; CHECK-GI-NEXT: and v0.16b, v0.16b, v3.16b
1757+
; CHECK-GI-NEXT: and v1.16b, v1.16b, v2.16b
17581758
; CHECK-GI-NEXT: mul v0.8h, v0.8h, v1.8h
17591759
; CHECK-GI-NEXT: ret
17601760
entry:

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