@@ -729,6 +729,7 @@ def CreateHandle : DXILOp<57, createHandle> {
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let arguments = [Int8Ty, Int32Ty, Int32Ty, Int1Ty];
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let result = HandleTy;
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let stages = [Stages<DXIL1_0, [all_stages]>, Stages<DXIL1_6, [removed]>];
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+ let attributes = [Attributes<DXIL1_0, [ReadOnly]>];
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}
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def BufferLoad : DXILOp<68, bufferLoad> {
@@ -740,6 +741,7 @@ def BufferLoad : DXILOp<68, bufferLoad> {
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[Overloads<DXIL1_0,
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[ResRetHalfTy, ResRetFloatTy, ResRetInt16Ty, ResRetInt32Ty]>];
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let stages = [Stages<DXIL1_0, [all_stages]>];
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+ let attributes = [Attributes<DXIL1_0, [ReadOnly]>];
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}
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def BufferStore : DXILOp<69, bufferStore> {
@@ -768,6 +770,7 @@ def CheckAccessFullyMapped : DXILOp<71, checkAccessFullyMapped> {
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let result = Int1Ty;
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let overloads = [Overloads<DXIL1_0, [Int32Ty]>];
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let stages = [Stages<DXIL1_0, [all_stages]>];
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+ let attributes = [Attributes<DXIL1_0, [ReadOnly]>];
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}
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def Discard : DXILOp<82, discard> {
@@ -833,8 +836,8 @@ def Dot4AddI8Packed : DXILOp<163, dot4AddPacked> {
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let LLVMIntrinsic = int_dx_dot4add_i8packed;
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let arguments = [Int32Ty, Int32Ty, Int32Ty];
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let result = Int32Ty;
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- let attributes = [Attributes<DXIL1_0, [ReadNone]>];
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let stages = [Stages<DXIL1_0, [all_stages]>];
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+ let attributes = [Attributes<DXIL1_0, [ReadNone]>];
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}
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def Dot4AddU8Packed : DXILOp<164, dot4AddPacked> {
@@ -843,22 +846,24 @@ def Dot4AddU8Packed : DXILOp<164, dot4AddPacked> {
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let LLVMIntrinsic = int_dx_dot4add_u8packed;
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let arguments = [Int32Ty, Int32Ty, Int32Ty];
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let result = Int32Ty;
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- let attributes = [Attributes<DXIL1_0, [ReadNone]>];
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let stages = [Stages<DXIL1_0, [all_stages]>];
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+ let attributes = [Attributes<DXIL1_0, [ReadNone]>];
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}
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def AnnotateHandle : DXILOp<216, annotateHandle> {
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let Doc = "annotate handle with resource properties";
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let arguments = [HandleTy, ResPropsTy];
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let result = HandleTy;
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let stages = [Stages<DXIL1_6, [all_stages]>];
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+ let attributes = [Attributes<DXIL1_0, [ReadNone]>];
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}
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def CreateHandleFromBinding : DXILOp<217, createHandleFromBinding> {
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let Doc = "create resource handle from binding";
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let arguments = [ResBindTy, Int32Ty, Int1Ty];
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let result = HandleTy;
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let stages = [Stages<DXIL1_6, [all_stages]>];
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+ let attributes = [Attributes<DXIL1_0, [ReadNone]>];
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}
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def WaveActiveAnyTrue : DXILOp<113, waveAnyTrue> {
@@ -875,7 +880,6 @@ def WaveIsFirstLane : DXILOp<110, waveIsFirstLane> {
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let arguments = [];
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let result = Int1Ty;
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let stages = [Stages<DXIL1_0, [all_stages]>];
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- let attributes = [Attributes<DXIL1_0, [ReadNone]>];
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}
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def WaveReadLaneAt: DXILOp<117, waveReadLaneAt> {
@@ -885,7 +889,6 @@ def WaveReadLaneAt: DXILOp<117, waveReadLaneAt> {
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let result = OverloadTy;
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let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy, DoubleTy, Int1Ty, Int16Ty, Int32Ty, Int64Ty]>];
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let stages = [Stages<DXIL1_0, [all_stages]>];
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- let attributes = [Attributes<DXIL1_0, [ReadNone]>];
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}
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def WaveGetLaneIndex : DXILOp<111, waveGetLaneIndex> {
@@ -894,7 +897,7 @@ def WaveGetLaneIndex : DXILOp<111, waveGetLaneIndex> {
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let arguments = [];
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let result = Int32Ty;
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let stages = [Stages<DXIL1_0, [all_stages]>];
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- let attributes = [Attributes<DXIL1_0, [ReadNone ]>];
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+ let attributes = [Attributes<DXIL1_0, [ReadOnly ]>];
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}
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def WaveAllBitCount : DXILOp<135, waveAllOp> {
@@ -903,5 +906,4 @@ def WaveAllBitCount : DXILOp<135, waveAllOp> {
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let arguments = [Int1Ty];
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let result = Int32Ty;
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let stages = [Stages<DXIL1_0, [all_stages]>];
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- let attributes = [Attributes<DXIL1_0, [ReadNone]>];
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}
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