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[DAG] canCreateUndefOrPoison - add FP_EXTEND (#152249)
Fixes #152141
1 parent 0b3ee20 commit 6ce68d3

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3 files changed

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-62
lines changed

3 files changed

+68
-62
lines changed

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5630,6 +5630,7 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts,
56305630
case ISD::FDIV:
56315631
case ISD::FREM:
56325632
case ISD::FCOPYSIGN:
5633+
case ISD::FP_EXTEND:
56335634
// No poison except from flags (which is handled above)
56345635
return false;
56355636

‎llvm/test/CodeGen/RISCV/half-convert.ll‎

Lines changed: 56 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -2262,12 +2262,12 @@ define i64 @fcvt_l_h_sat(half %a) nounwind {
22622262
; RV32IZHINX-NEXT: addi a2, a3, -1
22632263
; RV32IZHINX-NEXT: .LBB10_4: # %start
22642264
; RV32IZHINX-NEXT: feq.s a3, s0, s0
2265-
; RV32IZHINX-NEXT: neg a4, a1
2266-
; RV32IZHINX-NEXT: neg a1, s1
2265+
; RV32IZHINX-NEXT: neg a4, s1
2266+
; RV32IZHINX-NEXT: neg a5, a1
22672267
; RV32IZHINX-NEXT: neg a3, a3
2268-
; RV32IZHINX-NEXT: and a0, a1, a0
2268+
; RV32IZHINX-NEXT: and a0, a4, a0
22692269
; RV32IZHINX-NEXT: and a1, a3, a2
2270-
; RV32IZHINX-NEXT: or a0, a4, a0
2270+
; RV32IZHINX-NEXT: or a0, a5, a0
22712271
; RV32IZHINX-NEXT: and a0, a3, a0
22722272
; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
22732273
; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
@@ -2309,12 +2309,12 @@ define i64 @fcvt_l_h_sat(half %a) nounwind {
23092309
; RV32IZDINXZHINX-NEXT: addi a2, a3, -1
23102310
; RV32IZDINXZHINX-NEXT: .LBB10_4: # %start
23112311
; RV32IZDINXZHINX-NEXT: feq.s a3, s0, s0
2312-
; RV32IZDINXZHINX-NEXT: neg a4, a1
2313-
; RV32IZDINXZHINX-NEXT: neg a1, s1
2312+
; RV32IZDINXZHINX-NEXT: neg a4, s1
2313+
; RV32IZDINXZHINX-NEXT: neg a5, a1
23142314
; RV32IZDINXZHINX-NEXT: neg a3, a3
2315-
; RV32IZDINXZHINX-NEXT: and a0, a1, a0
2315+
; RV32IZDINXZHINX-NEXT: and a0, a4, a0
23162316
; RV32IZDINXZHINX-NEXT: and a1, a3, a2
2317-
; RV32IZDINXZHINX-NEXT: or a0, a4, a0
2317+
; RV32IZDINXZHINX-NEXT: or a0, a5, a0
23182318
; RV32IZDINXZHINX-NEXT: and a0, a3, a0
23192319
; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
23202320
; RV32IZDINXZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
@@ -2653,12 +2653,12 @@ define i64 @fcvt_l_h_sat(half %a) nounwind {
26532653
; CHECK32-IZHINXMIN-NEXT: addi a2, a3, -1
26542654
; CHECK32-IZHINXMIN-NEXT: .LBB10_4: # %start
26552655
; CHECK32-IZHINXMIN-NEXT: feq.s a3, s0, s0
2656-
; CHECK32-IZHINXMIN-NEXT: neg a4, a1
2657-
; CHECK32-IZHINXMIN-NEXT: neg a1, s1
2656+
; CHECK32-IZHINXMIN-NEXT: neg a4, s1
2657+
; CHECK32-IZHINXMIN-NEXT: neg a5, a1
26582658
; CHECK32-IZHINXMIN-NEXT: neg a3, a3
2659-
; CHECK32-IZHINXMIN-NEXT: and a0, a1, a0
2659+
; CHECK32-IZHINXMIN-NEXT: and a0, a4, a0
26602660
; CHECK32-IZHINXMIN-NEXT: and a1, a3, a2
2661-
; CHECK32-IZHINXMIN-NEXT: or a0, a4, a0
2661+
; CHECK32-IZHINXMIN-NEXT: or a0, a5, a0
26622662
; CHECK32-IZHINXMIN-NEXT: and a0, a3, a0
26632663
; CHECK32-IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
26642664
; CHECK32-IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
@@ -2701,12 +2701,12 @@ define i64 @fcvt_l_h_sat(half %a) nounwind {
27012701
; CHECK32-IZDINXZHINXMIN-NEXT: addi a2, a3, -1
27022702
; CHECK32-IZDINXZHINXMIN-NEXT: .LBB10_4: # %start
27032703
; CHECK32-IZDINXZHINXMIN-NEXT: feq.s a3, s0, s0
2704-
; CHECK32-IZDINXZHINXMIN-NEXT: neg a4, a1
2705-
; CHECK32-IZDINXZHINXMIN-NEXT: neg a1, s1
2704+
; CHECK32-IZDINXZHINXMIN-NEXT: neg a4, s1
2705+
; CHECK32-IZDINXZHINXMIN-NEXT: neg a5, a1
27062706
; CHECK32-IZDINXZHINXMIN-NEXT: neg a3, a3
2707-
; CHECK32-IZDINXZHINXMIN-NEXT: and a0, a1, a0
2707+
; CHECK32-IZDINXZHINXMIN-NEXT: and a0, a4, a0
27082708
; CHECK32-IZDINXZHINXMIN-NEXT: and a1, a3, a2
2709-
; CHECK32-IZDINXZHINXMIN-NEXT: or a0, a4, a0
2709+
; CHECK32-IZDINXZHINXMIN-NEXT: or a0, a5, a0
27102710
; CHECK32-IZDINXZHINXMIN-NEXT: and a0, a3, a0
27112711
; CHECK32-IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
27122712
; CHECK32-IZDINXZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
@@ -2972,18 +2972,19 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind {
29722972
; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
29732973
; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
29742974
; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
2975-
; RV32IZHINX-NEXT: fcvt.s.h a0, a0
2976-
; RV32IZHINX-NEXT: lui a1, 391168
2977-
; RV32IZHINX-NEXT: addi a1, a1, -1
2978-
; RV32IZHINX-NEXT: fle.s a2, zero, a0
2979-
; RV32IZHINX-NEXT: flt.s a1, a1, a0
2980-
; RV32IZHINX-NEXT: neg s0, a1
2981-
; RV32IZHINX-NEXT: neg s1, a2
2975+
; RV32IZHINX-NEXT: fcvt.s.h s0, a0
2976+
; RV32IZHINX-NEXT: fle.s a0, zero, s0
2977+
; RV32IZHINX-NEXT: neg s1, a0
2978+
; RV32IZHINX-NEXT: mv a0, s0
29822979
; RV32IZHINX-NEXT: call __fixunssfdi
29832980
; RV32IZHINX-NEXT: and a0, s1, a0
2981+
; RV32IZHINX-NEXT: lui a2, 391168
29842982
; RV32IZHINX-NEXT: and a1, s1, a1
2985-
; RV32IZHINX-NEXT: or a0, s0, a0
2986-
; RV32IZHINX-NEXT: or a1, s0, a1
2983+
; RV32IZHINX-NEXT: addi a2, a2, -1
2984+
; RV32IZHINX-NEXT: flt.s a2, a2, s0
2985+
; RV32IZHINX-NEXT: neg a2, a2
2986+
; RV32IZHINX-NEXT: or a0, a2, a0
2987+
; RV32IZHINX-NEXT: or a1, a2, a1
29872988
; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
29882989
; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
29892990
; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
@@ -3005,18 +3006,19 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind {
30053006
; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
30063007
; RV32IZDINXZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
30073008
; RV32IZDINXZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
3008-
; RV32IZDINXZHINX-NEXT: fcvt.s.h a0, a0
3009-
; RV32IZDINXZHINX-NEXT: lui a1, 391168
3010-
; RV32IZDINXZHINX-NEXT: addi a1, a1, -1
3011-
; RV32IZDINXZHINX-NEXT: fle.s a2, zero, a0
3012-
; RV32IZDINXZHINX-NEXT: flt.s a1, a1, a0
3013-
; RV32IZDINXZHINX-NEXT: neg s0, a1
3014-
; RV32IZDINXZHINX-NEXT: neg s1, a2
3009+
; RV32IZDINXZHINX-NEXT: fcvt.s.h s0, a0
3010+
; RV32IZDINXZHINX-NEXT: fle.s a0, zero, s0
3011+
; RV32IZDINXZHINX-NEXT: neg s1, a0
3012+
; RV32IZDINXZHINX-NEXT: mv a0, s0
30153013
; RV32IZDINXZHINX-NEXT: call __fixunssfdi
30163014
; RV32IZDINXZHINX-NEXT: and a0, s1, a0
3015+
; RV32IZDINXZHINX-NEXT: lui a2, 391168
30173016
; RV32IZDINXZHINX-NEXT: and a1, s1, a1
3018-
; RV32IZDINXZHINX-NEXT: or a0, s0, a0
3019-
; RV32IZDINXZHINX-NEXT: or a1, s0, a1
3017+
; RV32IZDINXZHINX-NEXT: addi a2, a2, -1
3018+
; RV32IZDINXZHINX-NEXT: flt.s a2, a2, s0
3019+
; RV32IZDINXZHINX-NEXT: neg a2, a2
3020+
; RV32IZDINXZHINX-NEXT: or a0, a2, a0
3021+
; RV32IZDINXZHINX-NEXT: or a1, a2, a1
30203022
; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
30213023
; RV32IZDINXZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
30223024
; RV32IZDINXZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
@@ -3217,18 +3219,19 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind {
32173219
; CHECK32-IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
32183220
; CHECK32-IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
32193221
; CHECK32-IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
3220-
; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0
3221-
; CHECK32-IZHINXMIN-NEXT: lui a1, 391168
3222-
; CHECK32-IZHINXMIN-NEXT: addi a1, a1, -1
3223-
; CHECK32-IZHINXMIN-NEXT: fle.s a2, zero, a0
3224-
; CHECK32-IZHINXMIN-NEXT: flt.s a1, a1, a0
3225-
; CHECK32-IZHINXMIN-NEXT: neg s0, a1
3226-
; CHECK32-IZHINXMIN-NEXT: neg s1, a2
3222+
; CHECK32-IZHINXMIN-NEXT: fcvt.s.h s0, a0
3223+
; CHECK32-IZHINXMIN-NEXT: fle.s a0, zero, s0
3224+
; CHECK32-IZHINXMIN-NEXT: neg s1, a0
3225+
; CHECK32-IZHINXMIN-NEXT: mv a0, s0
32273226
; CHECK32-IZHINXMIN-NEXT: call __fixunssfdi
32283227
; CHECK32-IZHINXMIN-NEXT: and a0, s1, a0
3228+
; CHECK32-IZHINXMIN-NEXT: lui a2, 391168
32293229
; CHECK32-IZHINXMIN-NEXT: and a1, s1, a1
3230-
; CHECK32-IZHINXMIN-NEXT: or a0, s0, a0
3231-
; CHECK32-IZHINXMIN-NEXT: or a1, s0, a1
3230+
; CHECK32-IZHINXMIN-NEXT: addi a2, a2, -1
3231+
; CHECK32-IZHINXMIN-NEXT: flt.s a2, a2, s0
3232+
; CHECK32-IZHINXMIN-NEXT: neg a2, a2
3233+
; CHECK32-IZHINXMIN-NEXT: or a0, a2, a0
3234+
; CHECK32-IZHINXMIN-NEXT: or a1, a2, a1
32323235
; CHECK32-IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
32333236
; CHECK32-IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
32343237
; CHECK32-IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
@@ -3251,18 +3254,19 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind {
32513254
; CHECK32-IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
32523255
; CHECK32-IZDINXZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
32533256
; CHECK32-IZDINXZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
3254-
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
3255-
; CHECK32-IZDINXZHINXMIN-NEXT: lui a1, 391168
3256-
; CHECK32-IZDINXZHINXMIN-NEXT: addi a1, a1, -1
3257-
; CHECK32-IZDINXZHINXMIN-NEXT: fle.s a2, zero, a0
3258-
; CHECK32-IZDINXZHINXMIN-NEXT: flt.s a1, a1, a0
3259-
; CHECK32-IZDINXZHINXMIN-NEXT: neg s0, a1
3260-
; CHECK32-IZDINXZHINXMIN-NEXT: neg s1, a2
3257+
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h s0, a0
3258+
; CHECK32-IZDINXZHINXMIN-NEXT: fle.s a0, zero, s0
3259+
; CHECK32-IZDINXZHINXMIN-NEXT: neg s1, a0
3260+
; CHECK32-IZDINXZHINXMIN-NEXT: mv a0, s0
32613261
; CHECK32-IZDINXZHINXMIN-NEXT: call __fixunssfdi
32623262
; CHECK32-IZDINXZHINXMIN-NEXT: and a0, s1, a0
3263+
; CHECK32-IZDINXZHINXMIN-NEXT: lui a2, 391168
32633264
; CHECK32-IZDINXZHINXMIN-NEXT: and a1, s1, a1
3264-
; CHECK32-IZDINXZHINXMIN-NEXT: or a0, s0, a0
3265-
; CHECK32-IZDINXZHINXMIN-NEXT: or a1, s0, a1
3265+
; CHECK32-IZDINXZHINXMIN-NEXT: addi a2, a2, -1
3266+
; CHECK32-IZDINXZHINXMIN-NEXT: flt.s a2, a2, s0
3267+
; CHECK32-IZDINXZHINXMIN-NEXT: neg a2, a2
3268+
; CHECK32-IZDINXZHINXMIN-NEXT: or a0, a2, a0
3269+
; CHECK32-IZDINXZHINXMIN-NEXT: or a1, a2, a1
32663270
; CHECK32-IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
32673271
; CHECK32-IZDINXZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
32683272
; CHECK32-IZDINXZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload

‎llvm/test/CodeGen/RISCV/rv64-half-convert.ll‎

Lines changed: 11 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -253,8 +253,8 @@ define i128 @fptosi_sat_f16_to_i128(half %a) nounwind {
253253
; RV64IZHINX-NEXT: srli a1, a2, 1
254254
; RV64IZHINX-NEXT: .LBB4_4:
255255
; RV64IZHINX-NEXT: feq.s a2, s0, s0
256-
; RV64IZHINX-NEXT: neg a3, a3
257256
; RV64IZHINX-NEXT: neg a4, s1
257+
; RV64IZHINX-NEXT: neg a3, a3
258258
; RV64IZHINX-NEXT: neg a2, a2
259259
; RV64IZHINX-NEXT: and a0, a4, a0
260260
; RV64IZHINX-NEXT: and a1, a2, a1
@@ -334,18 +334,19 @@ define i128 @fptoui_sat_f16_to_i128(half %a) nounwind {
334334
; RV64IZHINX-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
335335
; RV64IZHINX-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
336336
; RV64IZHINX-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
337-
; RV64IZHINX-NEXT: fcvt.s.h a0, a0
338-
; RV64IZHINX-NEXT: lui a1, 522240
339-
; RV64IZHINX-NEXT: addi a1, a1, -1
340-
; RV64IZHINX-NEXT: fle.s a2, zero, a0
341-
; RV64IZHINX-NEXT: flt.s a1, a1, a0
342-
; RV64IZHINX-NEXT: neg s0, a1
343-
; RV64IZHINX-NEXT: neg s1, a2
337+
; RV64IZHINX-NEXT: fcvt.s.h s0, a0
338+
; RV64IZHINX-NEXT: fle.s a0, zero, s0
339+
; RV64IZHINX-NEXT: neg s1, a0
340+
; RV64IZHINX-NEXT: mv a0, s0
344341
; RV64IZHINX-NEXT: call __fixunssfti
345342
; RV64IZHINX-NEXT: and a0, s1, a0
343+
; RV64IZHINX-NEXT: lui a2, 522240
346344
; RV64IZHINX-NEXT: and a1, s1, a1
347-
; RV64IZHINX-NEXT: or a0, s0, a0
348-
; RV64IZHINX-NEXT: or a1, s0, a1
345+
; RV64IZHINX-NEXT: addi a2, a2, -1
346+
; RV64IZHINX-NEXT: flt.s a2, a2, s0
347+
; RV64IZHINX-NEXT: neg a2, a2
348+
; RV64IZHINX-NEXT: or a0, a2, a0
349+
; RV64IZHINX-NEXT: or a1, a2, a1
349350
; RV64IZHINX-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
350351
; RV64IZHINX-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
351352
; RV64IZHINX-NEXT: ld s1, 8(sp) # 8-byte Folded Reload

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