Fix test cases, test register compatibility with regclass used

Author: JanekvO

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

@@ -2146,13 +2146,17 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
     Register DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
     Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
 
+    MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
+    auto *TRI = MRI.getTargetRegisterInfo();
+    const MCInstrDesc &Mov64Desc = get(AMDGPU::V_MOV_B64_e32);
+    const TargetRegisterClass *Mov64RC =
+        getRegClass(Mov64Desc, /*OpNum=*/0, TRI);
+
     const MachineOperand &SrcOp = MI.getOperand(1);
     // FIXME: Will this work for 64-bit floating point immediates?
     assert(!SrcOp.isFPImm());
-    MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
-    const TargetRegisterClass *RC = RI.getRegClassForReg(MRI, Dst);
-    if (ST.hasMovB64() && RI.isProperlyAlignedRC(*RC)) {
-      MI.setDesc(get(AMDGPU::V_MOV_B64_e32));
+    if (ST.hasMovB64() && Mov64RC->contains(Dst)) {
+      MI.setDesc(Mov64Desc);
       if (SrcOp.isReg() || isInlineConstant(MI, 1) ||
           isUInt<32>(SrcOp.getImm()) || ST.has64BitLiterals())
         break;
@@ -2161,18 +2165,22 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
       APInt Imm(64, SrcOp.getImm());
       APInt Lo(32, Imm.getLoBits(32).getZExtValue());
       APInt Hi(32, Imm.getHiBits(32).getZExtValue());
+      const MCInstrDesc &PkMovDesc = get(AMDGPU::V_PK_MOV_B32);
+      const TargetRegisterClass *PkMovRC =
+          getRegClass(PkMovDesc, /*OpNum=*/0, TRI);
+
       if (ST.hasPkMovB32() && Lo == Hi && isInlineConstant(Lo) &&
-          RI.isProperlyAlignedRC(*RC)) {
-        BuildMI(MBB, MI, DL, get(AMDGPU::V_PK_MOV_B32), Dst)
-          .addImm(SISrcMods::OP_SEL_1)
-          .addImm(Lo.getSExtValue())
-          .addImm(SISrcMods::OP_SEL_1)
-          .addImm(Lo.getSExtValue())
-          .addImm(0)  // op_sel_lo
-          .addImm(0)  // op_sel_hi
-          .addImm(0)  // neg_lo
-          .addImm(0)  // neg_hi
-          .addImm(0); // clamp
+          PkMovRC->contains(Dst)) {
+        BuildMI(MBB, MI, DL, PkMovDesc, Dst)
+            .addImm(SISrcMods::OP_SEL_1)
+            .addImm(Lo.getSExtValue())
+            .addImm(SISrcMods::OP_SEL_1)
+            .addImm(Lo.getSExtValue())
+            .addImm(0)  // op_sel_lo
+            .addImm(0)  // op_sel_hi
+            .addImm(0)  // neg_lo
+            .addImm(0)  // neg_hi
+            .addImm(0); // clamp
       } else {
         BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
           .addImm(Lo.getSExtValue())

llvm/test/CodeGen/AMDGPU/misaligned-vgpr-regsequence.mir

@@ -1,6 +1,6 @@
 # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -start-after=si-load-store-opt %s -o - | FileCheck %s
 
-# CHECK: "misaligned-regsequence":
+# CHECK: misaligned_regsequence:
 # CHECK: ; %bb.0:
 # CHECK:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 # CHECK:         s_load_dwordx2 s[0:1], s[4:5], 0x0
@@ -13,10 +13,10 @@
 # CHECK:         s_endpgm
 
 --- |
-  define void @misaligned-regsequence() { ret void }
+  define void @misaligned_regsequence() { ret void }
 ...
 ---
-name: misaligned-regsequence
+name: misaligned_regsequence
 tracksRegLiveness: true
 body:             |
   bb.0:

llvm/test/CodeGen/AMDGPU/v_mov_b64_expansion.mir

@@ -93,3 +93,12 @@ body: |
   bb.0:
     $vgpr0_vgpr1 = V_MOV_B64_PSEUDO 4575657222473777152, implicit $exec
 ...
+
+# GCN-LABEL: name: v_mov_b64_misalign
+# GCN: $vgpr5 = V_MOV_B32_e32 0, implicit $exec, implicit-def $vgpr5_vgpr6
+# GCN: $vgpr6 = V_MOV_B32_e32 0, implicit $exec, implicit-def $vgpr5_vgpr6
+name: v_mov_b64_misalign
+body: |
+  bb.0:
+    $vgpr5_vgpr6 = AV_MOV_B64_IMM_PSEUDO 0, implicit $exec
+...