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[Clang][AArch64] Move definitions of FP8 Neon loads & stores (#146352)
Moves the definitions of FP8 loads & stores so that they are guarded by `ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)"`
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‎clang/include/clang/Basic/arm_neon.td‎

Lines changed: 52 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -453,28 +453,28 @@ def VSLI_N : WInst<"vsli_n", "...I",
453453
////////////////////////////////////////////////////////////////////////////////
454454
// E.3.14 Loads and stores of a single vector
455455
def VLD1 : WInst<"vld1", ".(c*!)",
456-
"QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPsmQm">;
456+
"QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">;
457457
def VLD1_X2 : WInst<"vld1_x2", "2(c*!)",
458-
"cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPsmQm">;
458+
"cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
459459
def VLD1_X3 : WInst<"vld1_x3", "3(c*!)",
460-
"cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPsmQm">;
460+
"cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
461461
def VLD1_X4 : WInst<"vld1_x4", "4(c*!)",
462-
"cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPsmQm">;
462+
"cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
463463
def VLD1_LANE : WInst<"vld1_lane", ".(c*!).I",
464-
"QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPsmQm",
464+
"QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs",
465465
[ImmCheck<2, ImmCheckLaneIndex, 1>]>;
466466
def VLD1_DUP : WInst<"vld1_dup", ".(c*!)",
467-
"QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPsmQm">;
467+
"QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">;
468468
def VST1 : WInst<"vst1", "v*(.!)",
469-
"QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPsmQm">;
469+
"QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">;
470470
def VST1_X2 : WInst<"vst1_x2", "v*(2!)",
471-
"cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPsmQm">;
471+
"cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
472472
def VST1_X3 : WInst<"vst1_x3", "v*(3!)",
473-
"cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPsmQm">;
473+
"cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
474474
def VST1_X4 : WInst<"vst1_x4", "v*(4!)",
475-
"cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPsmQm">;
475+
"cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
476476
def VST1_LANE : WInst<"vst1_lane", "v*(.!)I",
477-
"QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPsmQm",
477+
"QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs",
478478
[ImmCheck<2, ImmCheckLaneIndex, 1>]>;
479479

480480
let ArchGuard = "(__ARM_FP & 2)" in {
@@ -495,29 +495,29 @@ def VST1_LANE_F16 : WInst<"vst1_lane", "v*(.!)I", "hQh",
495495

496496
////////////////////////////////////////////////////////////////////////////////
497497
// E.3.15 Loads and stores of an N-element structure
498-
def VLD2 : WInst<"vld2", "2(c*!)", "QUcQUsQUiQcQsQiQfQPcQPsUcUsUiUlcsilfPcPsmQm">;
499-
def VLD3 : WInst<"vld3", "3(c*!)", "QUcQUsQUiQcQsQiQfQPcQPsUcUsUiUlcsilfPcPsmQm">;
500-
def VLD4 : WInst<"vld4", "4(c*!)", "QUcQUsQUiQcQsQiQfQPcQPsUcUsUiUlcsilfPcPsmQm">;
498+
def VLD2 : WInst<"vld2", "2(c*!)", "QUcQUsQUiQcQsQiQfQPcQPsUcUsUiUlcsilfPcPs">;
499+
def VLD3 : WInst<"vld3", "3(c*!)", "QUcQUsQUiQcQsQiQfQPcQPsUcUsUiUlcsilfPcPs">;
500+
def VLD4 : WInst<"vld4", "4(c*!)", "QUcQUsQUiQcQsQiQfQPcQPsUcUsUiUlcsilfPcPs">;
501501
def VLD2_DUP : WInst<"vld2_dup", "2(c*!)",
502-
"UcUsUiUlcsilfPcPsQcQfQiQlQsQPcQPsQUcQUiQUlQUsmQm">;
502+
"UcUsUiUlcsilfPcPsQcQfQiQlQsQPcQPsQUcQUiQUlQUs">;
503503
def VLD3_DUP : WInst<"vld3_dup", "3(c*!)",
504-
"UcUsUiUlcsilfPcPsQcQfQiQlQsQPcQPsQUcQUiQUlQUsmQm">;
504+
"UcUsUiUlcsilfPcPsQcQfQiQlQsQPcQPsQUcQUiQUlQUs">;
505505
def VLD4_DUP : WInst<"vld4_dup", "4(c*!)",
506-
"UcUsUiUlcsilfPcPsQcQfQiQlQsQPcQPsQUcQUiQUlQUsmQm">;
507-
def VLD2_LANE : WInst<"vld2_lane", "2(c*!)2I", "QUsQUiQsQiQfQPsUcUsUicsifPcPsmQm",
506+
"UcUsUiUlcsilfPcPsQcQfQiQlQsQPcQPsQUcQUiQUlQUs">;
507+
def VLD2_LANE : WInst<"vld2_lane", "2(c*!)2I", "QUsQUiQsQiQfQPsUcUsUicsifPcPs",
508508
[ImmCheck<4, ImmCheckLaneIndex, 1>]>;
509-
def VLD3_LANE : WInst<"vld3_lane", "3(c*!)3I", "QUsQUiQsQiQfQPsUcUsUicsifPcPsmQm",
509+
def VLD3_LANE : WInst<"vld3_lane", "3(c*!)3I", "QUsQUiQsQiQfQPsUcUsUicsifPcPs",
510510
[ImmCheck<5, ImmCheckLaneIndex, 1>]>;
511-
def VLD4_LANE : WInst<"vld4_lane", "4(c*!)4I", "QUsQUiQsQiQfQPsUcUsUicsifPcPsmQm",
511+
def VLD4_LANE : WInst<"vld4_lane", "4(c*!)4I", "QUsQUiQsQiQfQPsUcUsUicsifPcPs",
512512
[ImmCheck<6, ImmCheckLaneIndex, 1>]>;
513-
def VST2 : WInst<"vst2", "v*(2!)", "QUcQUsQUiQcQsQiQfQPcQPsUcUsUiUlcsilfPcPsmQm">;
514-
def VST3 : WInst<"vst3", "v*(3!)", "QUcQUsQUiQcQsQiQfQPcQPsUcUsUiUlcsilfPcPsmQm">;
515-
def VST4 : WInst<"vst4", "v*(4!)", "QUcQUsQUiQcQsQiQfQPcQPsUcUsUiUlcsilfPcPsmQm">;
516-
def VST2_LANE : WInst<"vst2_lane", "v*(2!)I", "QUsQUiQsQiQfQPsUcUsUicsifPcPsmQm",
513+
def VST2 : WInst<"vst2", "v*(2!)", "QUcQUsQUiQcQsQiQfQPcQPsUcUsUiUlcsilfPcPs">;
514+
def VST3 : WInst<"vst3", "v*(3!)", "QUcQUsQUiQcQsQiQfQPcQPsUcUsUiUlcsilfPcPs">;
515+
def VST4 : WInst<"vst4", "v*(4!)", "QUcQUsQUiQcQsQiQfQPcQPsUcUsUiUlcsilfPcPs">;
516+
def VST2_LANE : WInst<"vst2_lane", "v*(2!)I", "QUsQUiQsQiQfQPsUcUsUicsifPcPs",
517517
[ImmCheck<3, ImmCheckLaneIndex, 1>]>;
518-
def VST3_LANE : WInst<"vst3_lane", "v*(3!)I", "QUsQUiQsQiQfQPsUcUsUicsifPcPsmQm",
518+
def VST3_LANE : WInst<"vst3_lane", "v*(3!)I", "QUsQUiQsQiQfQPsUcUsUicsifPcPs",
519519
[ImmCheck<4, ImmCheckLaneIndex, 1>]>;
520-
def VST4_LANE : WInst<"vst4_lane", "v*(4!)I", "QUsQUiQsQiQfQPsUcUsUicsifPcPsmQm",
520+
def VST4_LANE : WInst<"vst4_lane", "v*(4!)I", "QUsQUiQsQiQfQPsUcUsUicsifPcPs",
521521
[ImmCheck<5, ImmCheckLaneIndex, 1>]>;
522522
let ArchGuard = "(__ARM_FP & 2)" in {
523523
def VLD2_F16 : WInst<"vld2", "2(c*!)", "hQh">;
@@ -767,47 +767,47 @@ let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)" in {
767767

768768
////////////////////////////////////////////////////////////////////////////////
769769
// Load/Store
770-
def LD1 : WInst<"vld1", ".(c*!)", "dQdPlQPl">;
771-
def LD2 : WInst<"vld2", "2(c*!)", "QUlQldQdPlQPl">;
772-
def LD3 : WInst<"vld3", "3(c*!)", "QUlQldQdPlQPl">;
773-
def LD4 : WInst<"vld4", "4(c*!)", "QUlQldQdPlQPl">;
774-
def ST1 : WInst<"vst1", "v*(.!)", "dQdPlQPl">;
775-
def ST2 : WInst<"vst2", "v*(2!)", "QUlQldQdPlQPl">;
776-
def ST3 : WInst<"vst3", "v*(3!)", "QUlQldQdPlQPl">;
777-
def ST4 : WInst<"vst4", "v*(4!)", "QUlQldQdPlQPl">;
770+
def LD1 : WInst<"vld1", ".(c*!)", "dQdPlQPlmQm">;
771+
def LD2 : WInst<"vld2", "2(c*!)", "QUlQldQdPlQPlmQm">;
772+
def LD3 : WInst<"vld3", "3(c*!)", "QUlQldQdPlQPlmQm">;
773+
def LD4 : WInst<"vld4", "4(c*!)", "QUlQldQdPlQPlmQm">;
774+
def ST1 : WInst<"vst1", "v*(.!)", "dQdPlQPlmQm">;
775+
def ST2 : WInst<"vst2", "v*(2!)", "QUlQldQdPlQPlmQm">;
776+
def ST3 : WInst<"vst3", "v*(3!)", "QUlQldQdPlQPlmQm">;
777+
def ST4 : WInst<"vst4", "v*(4!)", "QUlQldQdPlQPlmQm">;
778778

779779
def LD1_X2 : WInst<"vld1_x2", "2(c*!)",
780-
"dQdPlQPl">;
780+
"dQdPlQPlmQm">;
781781
def LD1_X3 : WInst<"vld1_x3", "3(c*!)",
782-
"dQdPlQPl">;
782+
"dQdPlQPlmQm">;
783783
def LD1_X4 : WInst<"vld1_x4", "4(c*!)",
784-
"dQdPlQPl">;
784+
"dQdPlQPlmQm">;
785785

786-
def ST1_X2 : WInst<"vst1_x2", "v*(2!)", "dQdPlQPl">;
787-
def ST1_X3 : WInst<"vst1_x3", "v*(3!)", "dQdPlQPl">;
788-
def ST1_X4 : WInst<"vst1_x4", "v*(4!)", "dQdPlQPl">;
786+
def ST1_X2 : WInst<"vst1_x2", "v*(2!)", "dQdPlQPlmQm">;
787+
def ST1_X3 : WInst<"vst1_x3", "v*(3!)", "dQdPlQPlmQm">;
788+
def ST1_X4 : WInst<"vst1_x4", "v*(4!)", "dQdPlQPlmQm">;
789789

790-
def LD1_LANE : WInst<"vld1_lane", ".(c*!).I", "dQdPlQPl",
790+
def LD1_LANE : WInst<"vld1_lane", ".(c*!).I", "dQdPlQPlmQm",
791791
[ImmCheck<2, ImmCheckLaneIndex, 1>]>;
792-
def LD2_LANE : WInst<"vld2_lane", "2(c*!)2I", "lUlQcQUcQPcQlQUldQdPlQPl",
792+
def LD2_LANE : WInst<"vld2_lane", "2(c*!)2I", "lUlQcQUcQPcQlQUldQdPlQPlmQm",
793793
[ImmCheck<4, ImmCheckLaneIndex, 1>]>;
794-
def LD3_LANE : WInst<"vld3_lane", "3(c*!)3I", "lUlQcQUcQPcQlQUldQdPlQPl",
794+
def LD3_LANE : WInst<"vld3_lane", "3(c*!)3I", "lUlQcQUcQPcQlQUldQdPlQPlmQm",
795795
[ImmCheck<5, ImmCheckLaneIndex, 1>]>;
796-
def LD4_LANE : WInst<"vld4_lane", "4(c*!)4I", "lUlQcQUcQPcQlQUldQdPlQPl",
796+
def LD4_LANE : WInst<"vld4_lane", "4(c*!)4I", "lUlQcQUcQPcQlQUldQdPlQPlmQm",
797797
[ImmCheck<6, ImmCheckLaneIndex, 1>]>;
798-
def ST1_LANE : WInst<"vst1_lane", "v*(.!)I", "dQdPlQPl",
798+
def ST1_LANE : WInst<"vst1_lane", "v*(.!)I", "dQdPlQPlmQm",
799799
[ImmCheck<2, ImmCheckLaneIndex, 1>]>;
800-
def ST2_LANE : WInst<"vst2_lane", "v*(2!)I", "lUlQcQUcQPcQlQUldQdPlQPl",
800+
def ST2_LANE : WInst<"vst2_lane", "v*(2!)I", "lUlQcQUcQPcQlQUldQdPlQPlmQm",
801801
[ImmCheck<3, ImmCheckLaneIndex, 1>]>;
802-
def ST3_LANE : WInst<"vst3_lane", "v*(3!)I", "lUlQcQUcQPcQlQUldQdPlQPl",
802+
def ST3_LANE : WInst<"vst3_lane", "v*(3!)I", "lUlQcQUcQPcQlQUldQdPlQPlmQm",
803803
[ImmCheck<4, ImmCheckLaneIndex, 1>]>;
804-
def ST4_LANE : WInst<"vst4_lane", "v*(4!)I", "lUlQcQUcQPcQlQUldQdPlQPl",
804+
def ST4_LANE : WInst<"vst4_lane", "v*(4!)I", "lUlQcQUcQPcQlQUldQdPlQPlmQm",
805805
[ImmCheck<5, ImmCheckLaneIndex, 1>]>;
806806

807-
def LD1_DUP : WInst<"vld1_dup", ".(c*!)", "dQdPlQPl">;
808-
def LD2_DUP : WInst<"vld2_dup", "2(c*!)", "dQdPlQPl">;
809-
def LD3_DUP : WInst<"vld3_dup", "3(c*!)", "dQdPlQPl">;
810-
def LD4_DUP : WInst<"vld4_dup", "4(c*!)", "dQdPlQPl">;
807+
def LD1_DUP : WInst<"vld1_dup", ".(c*!)", "dQdPlQPlmQm">;
808+
def LD2_DUP : WInst<"vld2_dup", "2(c*!)", "dQdPlQPlmQm">;
809+
def LD3_DUP : WInst<"vld3_dup", "3(c*!)", "dQdPlQPlmQm">;
810+
def LD4_DUP : WInst<"vld4_dup", "4(c*!)", "dQdPlQPlmQm">;
811811

812812
def VLDRQ : WInst<"vldrq", "1(c*!)", "Pk">;
813813
def VSTRQ : WInst<"vstrq", "v*(1!)", "Pk">;

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