Skip to content

Commit 6d733fd

Browse files
artagnonartagnon
committed
[IR] Mark vector intrinsics speculatable, willreturn
The vector intrinsics in questions have no undefined behavior, and have no other effect besides returning the result, and do return a result: they should hence be marked speculatable and willreturn. At the moment, there are no optimizations that are enabled by these attributes, and the patch is mainly just documentation.
1 parent ed113e7 commit 6d733fd

File tree

3 files changed

+35
-14
lines changed

3 files changed

+35
-14
lines changed

‎llvm/include/llvm/IR/Intrinsics.td‎

Lines changed: 34 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -2422,12 +2422,12 @@ def int_loop_dependence_war_mask:
24222422
def int_get_active_lane_mask:
24232423
DefaultAttrsIntrinsic<[llvm_anyvector_ty],
24242424
[llvm_anyint_ty, LLVMMatchType<1>],
2425-
[IntrNoMem]>;
2425+
[IntrNoMem, IntrSpeculatable, IntrWillReturn]>;
24262426

24272427
def int_experimental_get_vector_length:
24282428
DefaultAttrsIntrinsic<[llvm_i32_ty],
24292429
[llvm_anyint_ty, llvm_i32_ty, llvm_i1_ty],
2430-
[IntrNoMem,
2430+
[IntrNoMem, IntrSpeculatable, IntrWillReturn,
24312431
ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
24322432

24332433
def int_experimental_cttz_elts:
@@ -2614,7 +2614,7 @@ def int_memset_element_unordered_atomic
26142614

26152615
//===------------------------ Reduction Intrinsics ------------------------===//
26162616
//
2617-
let IntrProperties = [IntrNoMem, IntrSpeculatable] in {
2617+
let IntrProperties = [IntrNoMem, IntrSpeculatable, IntrWillReturn] in {
26182618

26192619
def int_vector_reduce_fadd : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
26202620
[LLVMVectorElementType<0>,
@@ -2753,41 +2753,63 @@ def int_preserve_static_offset : DefaultAttrsIntrinsic<[llvm_ptr_ty],
27532753

27542754
def int_vector_reverse : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
27552755
[LLVMMatchType<0>],
2756-
[IntrNoMem]>;
2756+
[IntrNoMem,
2757+
IntrSpeculatable,
2758+
IntrWillReturn]>;
27572759

27582760
def int_vector_splice : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
27592761
[LLVMMatchType<0>,
27602762
LLVMMatchType<0>,
27612763
llvm_i32_ty],
2762-
[IntrNoMem, ImmArg<ArgIndex<2>>]>;
2764+
[IntrNoMem,
2765+
IntrSpeculatable,
2766+
IntrWillReturn,
2767+
ImmArg<ArgIndex<2>>]>;
27632768

27642769
//===---------- Intrinsics to query properties of scalable vectors --------===//
2765-
def int_vscale : DefaultAttrsIntrinsic<[llvm_anyint_ty], [], [IntrNoMem]>;
2770+
def int_vscale : DefaultAttrsIntrinsic<[llvm_anyint_ty],
2771+
[],
2772+
[IntrNoMem,
2773+
IntrSpeculatable,
2774+
IntrWillReturn]>;
27662775

27672776
//===---------- Intrinsics to perform subvector insertion/extraction ------===//
27682777
def int_vector_insert : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
27692778
[LLVMMatchType<0>, llvm_anyvector_ty, llvm_i64_ty],
2770-
[IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<2>>]>;
2779+
[IntrNoMem,
2780+
IntrSpeculatable,
2781+
IntrWillReturn,
2782+
ImmArg<ArgIndex<2>>]>;
27712783

27722784
def int_vector_extract : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
27732785
[llvm_anyvector_ty, llvm_i64_ty],
2774-
[IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<1>>]>;
2786+
[IntrNoMem,
2787+
IntrSpeculatable,
2788+
IntrWillReturn,
2789+
ImmArg<ArgIndex<1>>]>;
27752790

27762791
foreach n = 2...8 in {
27772792
def int_vector_interleave#n : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
27782793
!listsplat(LLVMOneNthElementsVectorType<0, n>, n),
2779-
[IntrNoMem]>;
2794+
[IntrNoMem,
2795+
IntrSpeculatable,
2796+
IntrWillReturn]>;
27802797

27812798
def int_vector_deinterleave#n : DefaultAttrsIntrinsic<!listsplat(LLVMOneNthElementsVectorType<0, n>, n),
27822799
[llvm_anyvector_ty],
2783-
[IntrNoMem]>;
2800+
[IntrNoMem,
2801+
IntrSpeculatable,
2802+
IntrWillReturn]>;
27842803
}
27852804

27862805
//===-------------- Intrinsics to perform partial reduction ---------------===//
27872806

27882807
def int_vector_partial_reduce_add : DefaultAttrsIntrinsic<[LLVMMatchType<0>],
2789-
[llvm_anyvector_ty, llvm_anyvector_ty],
2790-
[IntrNoMem]>;
2808+
[llvm_anyvector_ty,
2809+
llvm_anyvector_ty],
2810+
[IntrNoMem,
2811+
IntrSpeculatable,
2812+
IntrWillReturn]>;
27912813

27922814
//===----------------- Pointer Authentication Intrinsics ------------------===//
27932815
//

‎llvm/test/Transforms/LoopVectorize/RISCV/veclib-function-calls.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2288,7 +2288,7 @@ define void @tgamma_f32(ptr noalias %in.ptr, ptr noalias %out.ptr) {
22882288
}
22892289
;.
22902290
; CHECK: attributes #[[ATTR0]] = { "target-features"="+v" }
2291-
; CHECK: attributes #[[ATTR1:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(none) }
2291+
; CHECK: attributes #[[ATTR1:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
22922292
; CHECK: attributes #[[ATTR2]] = { "vector-function-abi-variant"="_ZGVrNxv_acos(Sleef_acosdx_u10rvvm2)" }
22932293
; CHECK: attributes #[[ATTR3]] = { "vector-function-abi-variant"="_ZGVrNxv_acosf(Sleef_acosfx_u10rvvm2)" }
22942294
; CHECK: attributes #[[ATTR4]] = { "vector-function-abi-variant"="_ZGVrNxv_acosh(Sleef_acoshdx_u10rvvm2)" }

‎llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-exp.ll‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -39,5 +39,4 @@ declare <4 x float> @llvm.exp.v4f32(<4 x float>) #0
3939
declare <vscale x 4 x float> @llvm.exp.nxv4f32(<vscale x 4 x float>) #0
4040

4141
; CHECK: attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
42-
; CHECK-NEXT: attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
4342
attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }

0 commit comments

Comments
 (0)