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[AMDGPU] Extend type support for update_dpp intrinsic (#114597)
We can split 64-bit DPP as a post-RA pseudo if control values are supported, but cannot handle other types.
1 parent dccb1fe commit 6d7e51d

12 files changed

+6178
-6104
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp‎

Lines changed: 29 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -5495,6 +5495,13 @@ bool AMDGPULegalizerInfo::legalizeLaneOp(LegalizerHelper &Helper,
54955495
}
54965496
case Intrinsic::amdgcn_mov_dpp8:
54975497
return LaneOp.addImm(MI.getOperand(3).getImm()).getReg(0);
5498+
case Intrinsic::amdgcn_update_dpp:
5499+
return LaneOp.addUse(Src1)
5500+
.addImm(MI.getOperand(4).getImm())
5501+
.addImm(MI.getOperand(5).getImm())
5502+
.addImm(MI.getOperand(6).getImm())
5503+
.addImm(MI.getOperand(7).getImm())
5504+
.getReg(0);
54985505
default:
54995506
llvm_unreachable("unhandled lane op");
55005507
}
@@ -5504,7 +5511,7 @@ bool AMDGPULegalizerInfo::legalizeLaneOp(LegalizerHelper &Helper,
55045511
Register Src0 = MI.getOperand(2).getReg();
55055512
Register Src1, Src2;
55065513
if (IID == Intrinsic::amdgcn_readlane || IID == Intrinsic::amdgcn_writelane ||
5507-
IsSetInactive || IsPermLane16) {
5514+
IID == Intrinsic::amdgcn_update_dpp || IsSetInactive || IsPermLane16) {
55085515
Src1 = MI.getOperand(3).getReg();
55095516
if (IID == Intrinsic::amdgcn_writelane || IsPermLane16) {
55105517
Src2 = MI.getOperand(4).getReg();
@@ -5514,15 +5521,21 @@ bool AMDGPULegalizerInfo::legalizeLaneOp(LegalizerHelper &Helper,
55145521
LLT Ty = MRI.getType(DstReg);
55155522
unsigned Size = Ty.getSizeInBits();
55165523

5517-
if (Size == 32) {
5524+
unsigned SplitSize = 32;
5525+
if (IID == Intrinsic::amdgcn_update_dpp && (Size % 64 == 0) &&
5526+
ST.hasDPALU_DPP() &&
5527+
AMDGPU::isLegalDPALU_DPPControl(MI.getOperand(4).getImm()))
5528+
SplitSize = 64;
5529+
5530+
if (Size == SplitSize) {
55185531
// Already legal
55195532
return true;
55205533
}
55215534

55225535
if (Size < 32) {
55235536
Src0 = B.buildAnyExt(S32, Src0).getReg(0);
55245537

5525-
if (IsSetInactive || IsPermLane16)
5538+
if (IID == Intrinsic::amdgcn_update_dpp || IsSetInactive || IsPermLane16)
55265539
Src1 = B.buildAnyExt(LLT::scalar(32), Src1).getReg(0);
55275540

55285541
if (IID == Intrinsic::amdgcn_writelane)
@@ -5534,31 +5547,28 @@ bool AMDGPULegalizerInfo::legalizeLaneOp(LegalizerHelper &Helper,
55345547
return true;
55355548
}
55365549

5537-
if (Size % 32 != 0)
5550+
if (Size % SplitSize != 0)
55385551
return false;
55395552

5540-
LLT PartialResTy = S32;
5553+
LLT PartialResTy = LLT::scalar(SplitSize);
55415554
if (Ty.isVector()) {
55425555
LLT EltTy = Ty.getElementType();
5543-
switch (EltTy.getSizeInBits()) {
5544-
case 16:
5545-
PartialResTy = Ty.changeElementCount(ElementCount::getFixed(2));
5546-
break;
5547-
case 32:
5556+
unsigned EltSize = EltTy.getSizeInBits();
5557+
if (EltSize == SplitSize) {
55485558
PartialResTy = EltTy;
5549-
break;
5550-
default:
5551-
// Handle all other cases via S32 pieces;
5552-
break;
5559+
} else if (EltSize == 16 || EltSize == 32) {
5560+
unsigned NElem = SplitSize / EltSize;
5561+
PartialResTy = Ty.changeElementCount(ElementCount::getFixed(NElem));
55535562
}
5563+
// Handle all other cases via S32/S64 pieces;
55545564
}
55555565

5556-
SmallVector<Register, 2> PartialRes;
5557-
unsigned NumParts = Size / 32;
5566+
SmallVector<Register, 4> PartialRes;
5567+
unsigned NumParts = Size / SplitSize;
55585568
MachineInstrBuilder Src0Parts = B.buildUnmerge(PartialResTy, Src0);
55595569
MachineInstrBuilder Src1Parts, Src2Parts;
55605570

5561-
if (IsSetInactive || IsPermLane16)
5571+
if (IID == Intrinsic::amdgcn_update_dpp || IsSetInactive || IsPermLane16)
55625572
Src1Parts = B.buildUnmerge(PartialResTy, Src1);
55635573

55645574
if (IID == Intrinsic::amdgcn_writelane)
@@ -5567,7 +5577,7 @@ bool AMDGPULegalizerInfo::legalizeLaneOp(LegalizerHelper &Helper,
55675577
for (unsigned i = 0; i < NumParts; ++i) {
55685578
Src0 = Src0Parts.getReg(i);
55695579

5570-
if (IsSetInactive || IsPermLane16)
5580+
if (IID == Intrinsic::amdgcn_update_dpp || IsSetInactive || IsPermLane16)
55715581
Src1 = Src1Parts.getReg(i);
55725582

55735583
if (IID == Intrinsic::amdgcn_writelane)
@@ -7555,6 +7565,7 @@ bool AMDGPULegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
75557565
case Intrinsic::amdgcn_set_inactive:
75567566
case Intrinsic::amdgcn_set_inactive_chain_arg:
75577567
case Intrinsic::amdgcn_mov_dpp8:
7568+
case Intrinsic::amdgcn_update_dpp:
75587569
return legalizeLaneOp(Helper, MI, IntrID);
75597570
case Intrinsic::amdgcn_s_buffer_prefetch_data:
75607571
return legalizeSBufferPrefetch(Helper, MI);

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp‎

Lines changed: 32 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -6162,13 +6162,20 @@ static SDValue lowerLaneOp(const SITargetLowering &TLI, SDNode *N,
61626162
IID == Intrinsic::amdgcn_set_inactive_chain_arg;
61636163
SDLoc SL(N);
61646164
MVT IntVT = MVT::getIntegerVT(ValSize);
6165+
const GCNSubtarget *ST = TLI.getSubtarget();
6166+
unsigned SplitSize = 32;
6167+
if (IID == Intrinsic::amdgcn_update_dpp && (ValSize % 64 == 0) &&
6168+
ST->hasDPALU_DPP() &&
6169+
AMDGPU::isLegalDPALU_DPPControl(N->getConstantOperandVal(3)))
6170+
SplitSize = 64;
61656171

61666172
auto createLaneOp = [&DAG, &SL, N, IID](SDValue Src0, SDValue Src1,
61676173
SDValue Src2, MVT ValT) -> SDValue {
61686174
SmallVector<SDValue, 8> Operands;
61696175
switch (IID) {
61706176
case Intrinsic::amdgcn_permlane16:
61716177
case Intrinsic::amdgcn_permlanex16:
6178+
case Intrinsic::amdgcn_update_dpp:
61726179
Operands.push_back(N->getOperand(6));
61736180
Operands.push_back(N->getOperand(5));
61746181
Operands.push_back(N->getOperand(4));
@@ -6206,13 +6213,15 @@ static SDValue lowerLaneOp(const SITargetLowering &TLI, SDNode *N,
62066213
SDValue Src0 = N->getOperand(1);
62076214
SDValue Src1, Src2;
62086215
if (IID == Intrinsic::amdgcn_readlane || IID == Intrinsic::amdgcn_writelane ||
6209-
IID == Intrinsic::amdgcn_mov_dpp8 || IsSetInactive || IsPermLane16) {
6216+
IID == Intrinsic::amdgcn_mov_dpp8 ||
6217+
IID == Intrinsic::amdgcn_update_dpp || IsSetInactive || IsPermLane16) {
62106218
Src1 = N->getOperand(2);
6211-
if (IID == Intrinsic::amdgcn_writelane || IsPermLane16)
6219+
if (IID == Intrinsic::amdgcn_writelane ||
6220+
IID == Intrinsic::amdgcn_update_dpp || IsPermLane16)
62126221
Src2 = N->getOperand(3);
62136222
}
62146223

6215-
if (ValSize == 32) {
6224+
if (ValSize == SplitSize) {
62166225
// Already legal
62176226
return SDValue();
62186227
}
@@ -6222,7 +6231,7 @@ static SDValue lowerLaneOp(const SITargetLowering &TLI, SDNode *N,
62226231
Src0 = DAG.getAnyExtOrTrunc(IsFloat ? DAG.getBitcast(IntVT, Src0) : Src0,
62236232
SL, MVT::i32);
62246233

6225-
if (IsSetInactive || IsPermLane16) {
6234+
if (IID == Intrinsic::amdgcn_update_dpp || IsSetInactive || IsPermLane16) {
62266235
Src1 = DAG.getAnyExtOrTrunc(IsFloat ? DAG.getBitcast(IntVT, Src1) : Src1,
62276236
SL, MVT::i32);
62286237
}
@@ -6237,7 +6246,7 @@ static SDValue lowerLaneOp(const SITargetLowering &TLI, SDNode *N,
62376246
return IsFloat ? DAG.getBitcast(VT, Trunc) : Trunc;
62386247
}
62396248

6240-
if (ValSize % 32 != 0)
6249+
if (ValSize % SplitSize != 0)
62416250
return SDValue();
62426251

62436252
auto unrollLaneOp = [&DAG, &SL](SDNode *N) -> SDValue {
@@ -6284,21 +6293,26 @@ static SDValue lowerLaneOp(const SITargetLowering &TLI, SDNode *N,
62846293
switch (MVT::SimpleValueType EltTy =
62856294
VT.getVectorElementType().getSimpleVT().SimpleTy) {
62866295
case MVT::i32:
6287-
case MVT::f32: {
6288-
SDValue LaneOp = createLaneOp(Src0, Src1, Src2, VT.getSimpleVT());
6289-
return unrollLaneOp(LaneOp.getNode());
6290-
}
6296+
case MVT::f32:
6297+
if (SplitSize == 32) {
6298+
SDValue LaneOp = createLaneOp(Src0, Src1, Src2, VT.getSimpleVT());
6299+
return unrollLaneOp(LaneOp.getNode());
6300+
}
6301+
[[fallthrough]];
62916302
case MVT::i16:
62926303
case MVT::f16:
62936304
case MVT::bf16: {
6294-
MVT SubVecVT = MVT::getVectorVT(EltTy, 2);
6305+
unsigned SubVecNumElt =
6306+
SplitSize / VT.getVectorElementType().getSizeInBits();
6307+
MVT SubVecVT = MVT::getVectorVT(EltTy, SubVecNumElt);
62956308
SmallVector<SDValue, 4> Pieces;
62966309
SDValue Src0SubVec, Src1SubVec, Src2SubVec;
6297-
for (unsigned i = 0, EltIdx = 0; i < ValSize / 32; i++) {
6310+
for (unsigned i = 0, EltIdx = 0; i < ValSize / SplitSize; i++) {
62986311
Src0SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, SubVecVT, Src0,
62996312
DAG.getConstant(EltIdx, SL, MVT::i32));
63006313

6301-
if (IsSetInactive || IsPermLane16)
6314+
if (IID == Intrinsic::amdgcn_update_dpp || IsSetInactive ||
6315+
IsPermLane16)
63026316
Src1SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, SubVecVT, Src1,
63036317
DAG.getConstant(EltIdx, SL, MVT::i32));
63046318

@@ -6307,10 +6321,10 @@ static SDValue lowerLaneOp(const SITargetLowering &TLI, SDNode *N,
63076321
DAG.getConstant(EltIdx, SL, MVT::i32));
63086322

63096323
Pieces.push_back(
6310-
IsSetInactive || IsPermLane16
6324+
IID == Intrinsic::amdgcn_update_dpp || IsSetInactive || IsPermLane16
63116325
? createLaneOp(Src0SubVec, Src1SubVec, Src2, SubVecVT)
63126326
: createLaneOp(Src0SubVec, Src1, Src2SubVec, SubVecVT));
6313-
EltIdx += 2;
6327+
EltIdx += SubVecNumElt;
63146328
}
63156329
return DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, Pieces);
63166330
}
@@ -6320,10 +6334,11 @@ static SDValue lowerLaneOp(const SITargetLowering &TLI, SDNode *N,
63206334
}
63216335
}
63226336

6323-
MVT VecVT = MVT::getVectorVT(MVT::i32, ValSize / 32);
6337+
MVT VecVT =
6338+
MVT::getVectorVT(MVT::getIntegerVT(SplitSize), ValSize / SplitSize);
63246339
Src0 = DAG.getBitcast(VecVT, Src0);
63256340

6326-
if (IsSetInactive || IsPermLane16)
6341+
if (IID == Intrinsic::amdgcn_update_dpp || IsSetInactive || IsPermLane16)
63276342
Src1 = DAG.getBitcast(VecVT, Src1);
63286343

63296344
if (IID == Intrinsic::amdgcn_writelane)
@@ -8833,6 +8848,7 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
88338848
case Intrinsic::amdgcn_set_inactive:
88348849
case Intrinsic::amdgcn_set_inactive_chain_arg:
88358850
case Intrinsic::amdgcn_mov_dpp8:
8851+
case Intrinsic::amdgcn_update_dpp:
88368852
return lowerLaneOp(*this, Op.getNode(), DAG);
88378853
default:
88388854
if (const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr =

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll‎

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -52,11 +52,11 @@ define amdgpu_kernel void @update_dppi64_test(ptr addrspace(1) %arg, i64 %in1, i
5252
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
5353
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
5454
; GFX8-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
55-
; GFX8-NEXT: v_mov_b32_e32 v5, s3
5655
; GFX8-NEXT: v_mov_b32_e32 v4, s2
56+
; GFX8-NEXT: v_mov_b32_e32 v5, s3
5757
; GFX8-NEXT: s_waitcnt vmcnt(0)
58-
; GFX8-NEXT: v_mov_b32_dpp v5, v3 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
5958
; GFX8-NEXT: v_mov_b32_dpp v4, v2 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
59+
; GFX8-NEXT: v_mov_b32_dpp v5, v3 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
6060
; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[4:5]
6161
; GFX8-NEXT: s_endpgm
6262
;
@@ -77,10 +77,10 @@ define amdgpu_kernel void @update_dppi64_test(ptr addrspace(1) %arg, i64 %in1, i
7777
; GFX11-LABEL: update_dppi64_test:
7878
; GFX11: ; %bb.0:
7979
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
80-
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
8180
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
82-
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
81+
; GFX11-NEXT: v_dual_mov_b32 v3, s3 :: v_dual_and_b32 v0, 0x3ff, v0
8382
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 3, v0
83+
; GFX11-NEXT: v_mov_b32_e32 v2, s2
8484
; GFX11-NEXT: global_load_b64 v[0:1], v4, s[0:1]
8585
; GFX11-NEXT: s_waitcnt vmcnt(0)
8686
; GFX11-NEXT: v_mov_b32_dpp v2, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
@@ -106,11 +106,11 @@ define amdgpu_kernel void @update_dppf64_test(ptr addrspace(1) %arg, double %in1
106106
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
107107
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
108108
; GFX8-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
109-
; GFX8-NEXT: v_mov_b32_e32 v5, s3
110109
; GFX8-NEXT: v_mov_b32_e32 v4, s2
110+
; GFX8-NEXT: v_mov_b32_e32 v5, s3
111111
; GFX8-NEXT: s_waitcnt vmcnt(0)
112-
; GFX8-NEXT: v_mov_b32_dpp v5, v3 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
113112
; GFX8-NEXT: v_mov_b32_dpp v4, v2 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
113+
; GFX8-NEXT: v_mov_b32_dpp v5, v3 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
114114
; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[4:5]
115115
; GFX8-NEXT: s_endpgm
116116
;
@@ -131,10 +131,10 @@ define amdgpu_kernel void @update_dppf64_test(ptr addrspace(1) %arg, double %in1
131131
; GFX11-LABEL: update_dppf64_test:
132132
; GFX11: ; %bb.0:
133133
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
134-
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
135134
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
136-
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
135+
; GFX11-NEXT: v_dual_mov_b32 v3, s3 :: v_dual_and_b32 v0, 0x3ff, v0
137136
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 3, v0
137+
; GFX11-NEXT: v_mov_b32_e32 v2, s2
138138
; GFX11-NEXT: global_load_b64 v[0:1], v4, s[0:1]
139139
; GFX11-NEXT: s_waitcnt vmcnt(0)
140140
; GFX11-NEXT: v_mov_b32_dpp v2, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
@@ -160,11 +160,11 @@ define amdgpu_kernel void @update_dppv2i32_test(ptr addrspace(1) %arg, <2 x i32>
160160
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
161161
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
162162
; GFX8-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
163-
; GFX8-NEXT: v_mov_b32_e32 v5, s3
164163
; GFX8-NEXT: v_mov_b32_e32 v4, s2
164+
; GFX8-NEXT: v_mov_b32_e32 v5, s3
165165
; GFX8-NEXT: s_waitcnt vmcnt(0)
166-
; GFX8-NEXT: v_mov_b32_dpp v5, v3 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
167166
; GFX8-NEXT: v_mov_b32_dpp v4, v2 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
167+
; GFX8-NEXT: v_mov_b32_dpp v5, v3 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
168168
; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[4:5]
169169
; GFX8-NEXT: s_endpgm
170170
;
@@ -185,10 +185,10 @@ define amdgpu_kernel void @update_dppv2i32_test(ptr addrspace(1) %arg, <2 x i32>
185185
; GFX11-LABEL: update_dppv2i32_test:
186186
; GFX11: ; %bb.0:
187187
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
188-
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
189188
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
190-
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
189+
; GFX11-NEXT: v_dual_mov_b32 v3, s3 :: v_dual_and_b32 v0, 0x3ff, v0
191190
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 3, v0
191+
; GFX11-NEXT: v_mov_b32_e32 v2, s2
192192
; GFX11-NEXT: global_load_b64 v[0:1], v4, s[0:1]
193193
; GFX11-NEXT: s_waitcnt vmcnt(0)
194194
; GFX11-NEXT: v_mov_b32_dpp v2, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
@@ -214,11 +214,11 @@ define amdgpu_kernel void @update_dppv2f32_test(ptr addrspace(1) %arg, <2 x floa
214214
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
215215
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
216216
; GFX8-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
217-
; GFX8-NEXT: v_mov_b32_e32 v5, s3
218217
; GFX8-NEXT: v_mov_b32_e32 v4, s2
218+
; GFX8-NEXT: v_mov_b32_e32 v5, s3
219219
; GFX8-NEXT: s_waitcnt vmcnt(0)
220-
; GFX8-NEXT: v_mov_b32_dpp v5, v3 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
221220
; GFX8-NEXT: v_mov_b32_dpp v4, v2 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
221+
; GFX8-NEXT: v_mov_b32_dpp v5, v3 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
222222
; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[4:5]
223223
; GFX8-NEXT: s_endpgm
224224
;
@@ -239,10 +239,10 @@ define amdgpu_kernel void @update_dppv2f32_test(ptr addrspace(1) %arg, <2 x floa
239239
; GFX11-LABEL: update_dppv2f32_test:
240240
; GFX11: ; %bb.0:
241241
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
242-
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
243242
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
244-
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
243+
; GFX11-NEXT: v_dual_mov_b32 v3, s3 :: v_dual_and_b32 v0, 0x3ff, v0
245244
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 3, v0
245+
; GFX11-NEXT: v_mov_b32_e32 v2, s2
246246
; GFX11-NEXT: global_load_b64 v[0:1], v4, s[0:1]
247247
; GFX11-NEXT: s_waitcnt vmcnt(0)
248248
; GFX11-NEXT: v_mov_b32_dpp v2, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
@@ -268,11 +268,11 @@ define amdgpu_kernel void @update_dpp_p0_test(ptr addrspace(1) %arg, ptr %in1, p
268268
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
269269
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
270270
; GFX8-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
271-
; GFX8-NEXT: v_mov_b32_e32 v5, s3
272271
; GFX8-NEXT: v_mov_b32_e32 v4, s2
272+
; GFX8-NEXT: v_mov_b32_e32 v5, s3
273273
; GFX8-NEXT: s_waitcnt vmcnt(0)
274-
; GFX8-NEXT: v_mov_b32_dpp v5, v3 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
275274
; GFX8-NEXT: v_mov_b32_dpp v4, v2 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
275+
; GFX8-NEXT: v_mov_b32_dpp v5, v3 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
276276
; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[4:5]
277277
; GFX8-NEXT: s_endpgm
278278
;
@@ -293,10 +293,10 @@ define amdgpu_kernel void @update_dpp_p0_test(ptr addrspace(1) %arg, ptr %in1, p
293293
; GFX11-LABEL: update_dpp_p0_test:
294294
; GFX11: ; %bb.0:
295295
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
296-
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
297296
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
298-
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
297+
; GFX11-NEXT: v_dual_mov_b32 v3, s3 :: v_dual_and_b32 v0, 0x3ff, v0
299298
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 3, v0
299+
; GFX11-NEXT: v_mov_b32_e32 v2, s2
300300
; GFX11-NEXT: global_load_b64 v[0:1], v4, s[0:1]
301301
; GFX11-NEXT: s_waitcnt vmcnt(0)
302302
; GFX11-NEXT: v_mov_b32_dpp v2, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1

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