Address review comments.

Author: mshahneo

mlir/include/mlir/Dialect/XeGPU/uArch/IntelGpuXe2.h

@@ -1,18 +1,19 @@
-//===--- IntelGpuXe2.h ---------------------------------------*- C++ -*-===//
+//===--- IntelGpuXe2.h ------------------------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
-/// \file
-/// Xe2 uArch definition.
-///
+// \file
+// Xe2 uArch definition. Xe2 is the second generation of Intel Xe GPUs.
+// This file defines the uArch details for Xe2 and its derived architectures.
+// This includes Ponte Vecchio (PVC) and Battlemage (BMG) architectures.
 //
 //===----------------------------------------------------------------------===//
-#ifndef MLIR_DIALECT_XEGPU_UARCH_INTEL_GPU_XE2_H
-#define MLIR_DIALECT_XEGPU_UARCH_INTEL_GPU_XE2_H
+#ifndef MLIR_DIALECT_XEGPU_UARCH_INTELGPUXE2_H
+#define MLIR_DIALECT_XEGPU_UARCH_INTELGPUXE2_H
 
 #include "mlir/Dialect/XeGPU/uArch/uArchInterfaces.h"
 #include "mlir/IR/BuiltinTypes.h"
@@ -179,4 +180,4 @@ struct BMGuArch : public Xe2Plus {
 } // namespace xegpu
 } // namespace mlir
 
-#endif // MLIR_DIALECT_XEGPU_UARCH_INTEL_GPU_XE2_H
+#endif // MLIR_DIALECT_XEGPU_UARCH_INTELGPUXE2H

mlir/include/mlir/Dialect/XeGPU/uArch/uArchBase.h

@@ -1,18 +1,18 @@
-//===--- uArch.h ---------------------------------------*- C++ -*-===//
+//===--- uArch.h ------------------------------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
-/// \file
-/// Base uArch definition for different architectures.
-///
+// \file
+// Base uArch definition for different architectures.
+//
 //
 //===----------------------------------------------------------------------===//
-#ifndef MLIR_DIALECT_XEGPU_UARCH_BASE_H
-#define MLIR_DIALECT_XEGPU_UARCH_BASE_H
+#ifndef MLIR_DIALECT_XEGPU_UARCH_UARCHBASE_H
+#define MLIR_DIALECT_XEGPU_UARCH_UARCHBASE_H
 
 #include <any>
 #include <functional>
@@ -263,4 +263,4 @@ struct uArchMap {
 } // namespace xegpu
 } // namespace mlir
 
-#endif // MLIR_DIALECT_XEGPU_UARCH_BASE_H
+#endif // MLIR_DIALECT_XEGPU_UARCH_UARCHBASE_H

mlir/lib/Dialect/XeGPU/uArch/IntelGpuXe2.cpp

@@ -1,11 +1,11 @@
 #include "mlir/Dialect/XeGPU/uArch/IntelGpuXe2.h"
 #include "mlir/IR/BuiltinTypes.h"
-#include "llvm/Support/YAMLTraits.h"
+#include "llvm/Support/DebugLog.h"
 #include <algorithm>
-#include <iostream>
-#include <string>
 #include <vector>
 
+#define DEBUG_TYPE "xegpu-uarch"
+
 using namespace mlir::xegpu::uArch;
 using namespace mlir::xegpu::uArch::Xe2Plus;
 
@@ -80,51 +80,26 @@ bool DPASInstruction::checkSupportedTypes(mlir::Type AType, mlir::Type BType,
   if (AType.isF16() || BType.isF16()) {
     if (AType != BType || (CType && (!CType.isF32() && !CType.isF16())) ||
         (!DType.isF32() && !DType.isF16())) {
-      llvm::errs()
-          << "Unsupported dpas combinations of Dst, Acc, A and B matrices, "
-          << "Supported types are:\n"
-          << "  Dst    |   Acc   |   A   |  B  \n"
-          << " f, hf   |  f, hf  |   hf  |  hf \n"
-          << "AType: " << AType << " BType: " << BType << " CType: " << CType
-          << " DType: " << DType;
+      LDBG() << "Unsupported dpas combinations of Dst, Acc, A and B matrices.";
       return false;
     }
   } else if (AType.isBF16() || BType.isBF16()) {
     if (AType != BType || (CType && (!CType.isF32() && !CType.isBF16())) ||
         (!DType.isF32() && !DType.isBF16())) {
-      llvm::errs()
-          << "Unsupported dpas combinations of Dst, Acc, A and B matrices, "
-          << "Supported types are:\n"
-          << "  Dst    |   Acc   |   A   |  B  \n"
-          << " f, bf   |  f, bf  |   bf  |  bf \n"
-          << "AType: " << AType << " BType: " << BType << " CType: " << CType
-          << " DType: " << DType;
+      LDBG() << "Unsupported dpas combinations of Dst, Acc, A and B matrices.";
       return false;
     }
   } else if (AType.isTF32() || BType.isTF32()) {
     if (AType != BType || (CType && (!CType.isF32() && !DType.isF32())) ||
         (!DType.isF32())) {
-      llvm::errs()
-          << "Unsupported dpas combinations of Dst, Acc, A and B matrices, "
-          << "Supported types are:\n"
-          << "  Dst    |   Acc   |   A    |   B  \n"
-          << "   f     |    f    |  tf32  |  tf32 \n"
-          << "AType: " << AType << " BType: " << BType << " CType: " << CType
-          << " DType: " << DType;
+      LDBG() << "Unsupported dpas combinations of Dst, Acc, A and B matrices.";
       return false;
     }
   } else if (!(AType.isInteger(2) || AType.isInteger(4) ||
                AType.isInteger(8)) &&
              !(BType.isInteger(2) || BType.isInteger(4) ||
                BType.isInteger(8))) {
-    llvm::errs()
-        << "Unsupported dpas combinations of Dst, Acc, A and B matrices, "
-        << "Supported types are:\n"
-        << "  Dst     |   Acc    |         A           |         B          "
-           " \n"
-        << " ud, d    |  ud,d    |  ub,b,u4,s4,u2,s2   |  ub,b,u4,s4,u2,s2  "
-        << "AType: " << AType << " BType: " << BType << " CType: " << CType
-        << " DType: " << DType;
+    LDBG() << "Unsupported dpas combinations of Dst, Acc, A and B matrices.";
     return false;
   }