[RISCV] Fix formatting

pfusik · pfusik · commit 6df53351b7b1 · 2025-01-13T14:00:38.000+01:00
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -17412,10 +17412,9 @@ static SDValue combineSHL(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
   default:
     llvm_unreachable("Expected SHL");
   }
-  return DAG.getNode(
-      Opcode, DL, VT, NarrowOp,
-      DAG.getConstant(1ULL << ShAmtInt, SDLoc(RHS), NarrowVT),
-      Passthru, Mask, VL);
+  return DAG.getNode(Opcode, DL, VT, NarrowOp,
+                     DAG.getConstant(1ULL << ShAmtInt, SDLoc(RHS), NarrowVT),
+                     Passthru, Mask, VL);
 }
 
 SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,

Original file line number	Diff line number	Diff line change
`@@ -17412,10 +17412,9 @@ static SDValue combineSHL(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,`
`17412`	`17412`	`default:`
`17413`	`17413`	`llvm_unreachable("Expected SHL");`
`17414`	`17414`	`}`
`17415`		`- return DAG.getNode(`
`17416`		`- Opcode, DL, VT, NarrowOp,`
`17417`		`- DAG.getConstant(1ULL << ShAmtInt, SDLoc(RHS), NarrowVT),`
`17418`		`- Passthru, Mask, VL);`
	`17415`	`+ return DAG.getNode(Opcode, DL, VT, NarrowOp,`
	`17416`	`+ DAG.getConstant(1ULL << ShAmtInt, SDLoc(RHS), NarrowVT),`
	`17417`	`+ Passthru, Mask, VL);`
`17419`	`17418`	`}`
`17420`	`17419`
`17421`	`17420`	`SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,`