Address review comments

Author: peterbell10

llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp

@@ -2319,39 +2319,39 @@ SDValue NVPTXTargetLowering::LowerBITCAST(SDValue Op, SelectionDAG &DAG) const {
   // Handle bitcasting to/from v2i8 without hitting the default promotion
   // strategy which goes through stack memory.
   SDNode *Node = Op.getNode();
-  SDLoc dl(Node);
+  SDLoc DL(Node);
 
-  auto maybeBitcast = [&](EVT vt, SDValue val) {
-    if (val->getValueType(0) == vt) {
-      return val;
-    }
-    return DAG.getNode(ISD::BITCAST, dl, vt, val);
+  auto maybeBitcast = [&](EVT VT, SDValue Value) {
+    if (Value->getValueType(0) == VT)
+      return Value;
+    return DAG.getNode(ISD::BITCAST, DL, VT, Value);
   };
 
-  EVT VT = Op->getValueType(0);
-  EVT fromVT = Op->getOperand(0)->getValueType(0);
+  EVT ToVT = Op->getValueType(0);
+  EVT FromVT = Op->getOperand(0)->getValueType(0);
 
-  if (VT == MVT::v2i8) {
+  if (ToVT == MVT::v2i8) {
     // Bitcast to i16 and unpack elements into a vector
-    SDValue reg = maybeBitcast(MVT::i16, Op->getOperand(0));
-    SDValue v0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, reg);
-    SDValue C8 = DAG.getConstant(8, dl, MVT::i16);
-    SDValue v1 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
-                             DAG.getNode(ISD::SRL, dl, MVT::i16, {reg, C8}));
-    return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i8, {v0, v1});
-  } else if (fromVT == MVT::v2i8) {
+    SDValue AsInt = maybeBitcast(MVT::i16, Op->getOperand(0));
+    SDValue Vec0 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, AsInt);
+    SDValue Const8 = DAG.getConstant(8, DL, MVT::i16);
+    SDValue Vec1 =
+        DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
+                    DAG.getNode(ISD::SRL, DL, MVT::i16, {AsInt, Const8}));
+    return DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2i8, {Vec0, Vec1});
+  } else if (FromVT == MVT::v2i8) {
     // Pack vector elements into i16 and bitcast to final type
-    SDValue v0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i8,
-                             Op->getOperand(0), DAG.getIntPtrConstant(0, dl));
-    SDValue v1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i8,
-                             Op->getOperand(0), DAG.getIntPtrConstant(1, dl));
-    SDValue E0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, v0);
-    SDValue E1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, v1);
-    SDValue C8 = DAG.getConstant(8, dl, MVT::i16);
-    SDValue reg =
-        DAG.getNode(ISD::OR, dl, MVT::i16,
-                    {E0, DAG.getNode(ISD::SHL, dl, MVT::i16, {E1, C8})});
-    return maybeBitcast(VT, reg);
+    SDValue Vec0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i8,
+                               Op->getOperand(0), DAG.getIntPtrConstant(0, DL));
+    SDValue Vec1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i8,
+                               Op->getOperand(0), DAG.getIntPtrConstant(1, DL));
+    SDValue Extend0 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i16, Vec0);
+    SDValue Extend1 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i16, Vec1);
+    SDValue Const8 = DAG.getConstant(8, DL, MVT::i16);
+    SDValue AsInt = DAG.getNode(
+        ISD::OR, DL, MVT::i16,
+        {Extend0, DAG.getNode(ISD::SHL, DL, MVT::i16, {Extend1, Const8})});
+    return maybeBitcast(ToVT, AsInt);
   }
   return Op;
 }

llvm/test/CodeGen/NVPTX/i8x2-instructions.ll

@@ -9,28 +9,25 @@
 
 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 
-; CHECK-LABEL: test_trunc_2xi8(
-; CHECK:      ld.param.u32 [[R1:%r[0-9]+]], [test_trunc_2xi8_param_0];
-; CHECK:      mov.b32 {[[RS1:%rs[0-9]+]], [[RS2:%rs[0-9]+]]}, [[R1]];
-; CHECK:      shl.b16 	[[RS3:%rs[0-9]+]], [[RS2]], 8;
-; CHECK:      and.b16  [[RS4:%rs[0-9]+]], [[RS1]], 255;
-; CHECK:      or.b16   [[RS5:%rs[0-9]+]], [[RS4]], [[RS3]]
-; CHECK:      cvt.u32.u16  [[R2:%r[0-9]]], [[RS5]]
-; CHECK:      st.param.b32  [func_retval0], [[R2]];
-define i16 @test_trunc_2xi8(<2 x i16> %a) #0 {
-  %trunc = trunc <2 x i16> %a to <2 x i8>
-  %res = bitcast <2 x i8> %trunc to i16
+; CHECK-LABEL: test_bitcast_2xi8_i16(
+; CHECK: ld.param.u32 	%r1, [test_bitcast_2xi8_i16_param_0];
+; CHECK: mov.b32 	{%rs1, %rs2}, %r1;
+; CHECK: shl.b16 	%rs3, %rs2, 8;
+; CHECK: and.b16  	%rs4, %rs1, 255;
+; CHECK: or.b16  	%rs5, %rs4, %rs3;
+; CHECK: cvt.u32.u16 	%r2, %rs5;
+; CHECK: st.param.b32 	[func_retval0], %r2;
+define i16 @test_bitcast_2xi8_i16(<2 x i8> %a) {
+  %res = bitcast <2 x i8> %a to i16
   ret i16 %res
 }
 
-; CHECK-LABEL: test_zext_2xi8(
-; CHECK:      ld.param.u16  [[RS1:%rs[0-9]+]], [test_zext_2xi8_param_0];
-; CHECK:      shr.u16 	[[RS2:%rs[0-9]+]], [[RS1]], 8;
-; CHECK:      mov.b32  [[R1:%r[0-9]+]], {[[RS1]], [[RS2]]}
-; CHECK:      and.b32  [[R2:%r[0-9]+]], [[R1]], 16711935;
-; CHECK:      st.param.b32  [func_retval0], [[R2]];
-define <2 x i16> @test_zext_2xi8(i16 %a) #0 {
-  %vec = bitcast i16 %a to <2 x i8>
-  %ext = zext <2 x i8> %vec to <2 x i16>
-  ret <2 x i16> %ext
+; CHECK-LABEL: test_bitcast_i16_2xi8(
+; CHECK: ld.param.u16 	%rs1, [test_bitcast_i16_2xi8_param_0];
+; CHECK: shr.u16 	%rs2, %rs1, 8;
+; CHECK: mov.b32 	%r1, {%rs1, %rs2};
+; CHECK: st.param.b32 	[func_retval0], %r1;
+define <2 x i8> @test_bitcast_i16_2xi8(i16 %a) {
+  %res = bitcast i16 %a to <2 x i8>
+  ret <2 x i8> %res
 }