[M68k] Fix backwards BTST condition

dansalvato · dansalvato · commit 6e5bffbe4ff3 · 2025-08-11T15:16:49.000-06:00
diff --git a/llvm/lib/Target/M68k/M68kISelLowering.cpp b/llvm/lib/Target/M68k/M68kISelLowering.cpp
@@ -1667,8 +1667,8 @@ static SDValue getBitTestCondition(SDValue Src, SDValue BitNo, ISD::CondCode CC,
 
   SDValue BTST = DAG.getNode(M68kISD::BTST, DL, MVT::i32, Src, BitNo);
 
-  // NOTE BTST sets CCR.Z flag
-  M68k::CondCode Cond = CC == ISD::SETEQ ? M68k::COND_NE : M68k::COND_EQ;
+  // NOTE BTST sets CCR.Z flag if bit is 0, same as AND with bitmask
+  M68k::CondCode Cond = CC == ISD::SETEQ ? M68k::COND_EQ : M68k::COND_NE;
   return DAG.getNode(M68kISD::SETCC, DL, MVT::i8,
                      DAG.getConstant(Cond, DL, MVT::i8), BTST);
 }

Original file line number	Diff line number	Diff line change
`@@ -1667,8 +1667,8 @@ static SDValue getBitTestCondition(SDValue Src, SDValue BitNo, ISD::CondCode CC,`
`1667`	`1667`
`1668`	`1668`	`SDValue BTST = DAG.getNode(M68kISD::BTST, DL, MVT::i32, Src, BitNo);`
`1669`	`1669`
`1670`		`- // NOTE BTST sets CCR.Z flag`
`1671`		`- M68k::CondCode Cond = CC == ISD::SETEQ ? M68k::COND_NE : M68k::COND_EQ;`
	`1670`	`+ // NOTE BTST sets CCR.Z flag if bit is 0, same as AND with bitmask`
	`1671`	`+ M68k::CondCode Cond = CC == ISD::SETEQ ? M68k::COND_EQ : M68k::COND_NE;`
`1672`	`1672`	`return DAG.getNode(M68kISD::SETCC, DL, MVT::i8,`
`1673`	`1673`	`DAG.getConstant(Cond, DL, MVT::i8), BTST);`
`1674`	`1674`	`}`