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Author: daniilavdeev

lldb/include/lldb/Core/EmulateInstruction.h

@@ -46,7 +46,8 @@ class SingleStepBreakpointLocationsPredictor {
 
   virtual BreakpointLocations GetBreakpointLocations(Status &status);
 
-  virtual llvm::Expected<unsigned> GetBreakpointSize(lldb::addr_t bp_addr) {
+  virtual llvm::Expected<unsigned>
+  GetBreakpointSize([[maybe_unused]] lldb::addr_t bp_addr) {
     return 4;
   }
 

lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp

@@ -1843,7 +1843,8 @@ RISCVSingleStepBreakpointLocationsPredictor::HandleAtomicSequence(
   // RISC-V ISA there can be at most 16 instructions in the sequence.
 
   lldb::addr_t entry_pc = pc; // LR instruction address
-  pc += 4;                    // add LR_W, LR_D instruction size
+  auto lr_inst = riscv_emulator->ReadInstructionAt(entry_pc);
+  pc += lr_inst->is_rvc ? 2 : 4;
 
   size_t atomic_length = 0;
   std::optional<DecodeResult> inst;
@@ -1873,7 +1874,7 @@ RISCVSingleStepBreakpointLocationsPredictor::HandleAtomicSequence(
               "RISCVSingleStepBreakpointLocationsPredictor::%s: can't find "
               "corresponding store conditional insturuction",
               __FUNCTION__);
-    return {entry_pc + 4};
+    return {entry_pc + lr_inst->is_rvc ? 2u : 4u};
   }
 
   lldb::addr_t exit_pc = pc;

lldb/test/API/riscv/step/TestSoftwareStep.py

@@ -1,5 +1,6 @@
 """
 Test software step-inst, also known as instruction level single step, in risc-v atomic sequence.
+For more information about atomic sequences, see the RISC-V Unprivileged ISA specification.
 """
 
 import lldb

lldb/test/API/riscv/step/branch.c

@@ -1,4 +1,7 @@
 void __attribute__((naked)) branch_cas(int *a, int *b) {
+  // Stop at the first instruction. The atomic sequence contains active forward
+  // branch (bne a5, a1, 2f). After step instruction lldb should stop at the
+  // branch's target address (ret instruction).
   asm volatile("1:\n\t"
                "lr.w a2, (a0)\n\t"
                "and a5, a2, a4\n\t"

lldb/test/API/riscv/step/incomplete_sequence_without_lr.c

@@ -1,4 +1,7 @@
 void __attribute__((naked)) incomplete_cas(int *a, int *b) {
+  // Stop at the first instruction (an sc without a corresponding lr), then make
+  // a step instruction and ensure that execution stops at the next instruction
+  // (and).
   asm volatile("1:\n\t"
                "sc.w a5, a1, (a3)\n\t"
                "and a5, a2, a4\n\t"

lldb/test/API/riscv/step/incomplete_sequence_without_sc.c

@@ -1,4 +1,7 @@
 void __attribute__((naked)) incomplete_cas(int *a, int *b) {
+  // Stop at the first instruction (an lr without a corresponding sc), then make
+  // a step instruction and ensure that execution stops at the next instruction
+  // (and).
   asm volatile("1:\n\t"
                "lr.w a2, (a0)\n\t"
                "and a5, a2, a4\n\t"

lldb/test/API/riscv/step/main.c

@@ -1,4 +1,7 @@
 void __attribute__((naked)) cas(int *a, int *b) {
+  // This atomic sequence implements a copy-and-swap function. This test should
+  // at the first instruction, and after step instruction, we should stop at the
+  // end of the sequence (on the ret instruction).
   asm volatile("1:\n\t"
                "lr.w a2, (a0)\n\t"
                "and a5, a2, a4\n\t"