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4 files changed

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‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8622,7 +8622,7 @@ SDValue SITargetLowering::lowerWorkitemID(SelectionDAG &DAG, SDValue Op,
86228622
// It's undefined behavior if a function marked with the amdgpu-no-*
86238623
// attributes uses the corresponding intrinsic.
86248624
if (!Arg)
8625-
return DAG.getUNDEF(EVT::getIntegerVT(*DAG.getContext(), 32));
8625+
return DAG.getUNDEF(Op->getValueType(0));
86268626

86278627
SDValue Val = loadInputValue(DAG, &AMDGPU::VGPR_32RegClass, MVT::i32,
86288628
SDLoc(DAG.getEntryNode()), Arg);

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll‎

Lines changed: 0 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,6 @@
99
; RUN: llc -global-isel -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx90a -verify-machineinstrs < %t.v4.ll | FileCheck -check-prefixes=ALL,PACKED-TID %s
1010
; RUN: llc -global-isel -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx1100 -verify-machineinstrs -amdgpu-enable-vopd=0 < %t.v4.ll | FileCheck -check-prefixes=ALL,PACKED-TID %s
1111
; RUN: llc -global-isel -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=6 -mcpu=gfx11-generic -verify-machineinstrs -amdgpu-enable-vopd=0 < %t.v6.ll | FileCheck -check-prefixes=ALL,PACKED-TID %s
12-
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx942 -o - %t.v4.ll | FileCheck --check-prefixes=UNDEF %s
1312

1413
declare i32 @llvm.amdgcn.workitem.id.x() #0
1514
declare i32 @llvm.amdgcn.workitem.id.y() #0
@@ -196,30 +195,6 @@ define amdgpu_kernel void @test_reqd_workgroup_size_z_only(ptr %out) !reqd_work_
196195
ret void
197196
}
198197

199-
define amdgpu_kernel void @undefined_workitem_x_only() {
200-
; UNDEF-LABEL: undefined_workitem_x_only:
201-
; UNDEF: ; %bb.0:
202-
; UNDEF-NEXT: s_endpgm
203-
%id.x = call i32 @llvm.amdgcn.workitem.id.x()
204-
ret void
205-
}
206-
207-
define amdgpu_kernel void @undefined_workitem_y_only() {
208-
; UNDEF-LABEL: undefined_workitem_y_only:
209-
; UNDEF: ; %bb.0:
210-
; UNDEF-NEXT: s_endpgm
211-
%id.y = call i32 @llvm.amdgcn.workitem.id.y()
212-
ret void
213-
}
214-
215-
define amdgpu_kernel void @undefined_workitem_z_only() {
216-
; UNDEF-LABEL: undefined_workitem_z_only:
217-
; UNDEF: ; %bb.0:
218-
; UNDEF-NEXT: s_endpgm
219-
%id.z = call i32 @llvm.amdgcn.workitem.id.z()
220-
ret void
221-
}
222-
223198
attributes #0 = { nounwind readnone }
224199
attributes #1 = { nounwind }
225200

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id-unsupported-calling-convention.ll‎

Lines changed: 61 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,61 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc -mtriple=amdgcn -mcpu=gfx942 -O0 -stop-after=si-fix-sgpr-copies -o - %s | FileCheck --check-prefix=SelDAG %s
3+
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx942 -stop-after=legalizer -o - %s | FileCheck --check-prefix=GlobalISel %s
4+
5+
declare i32 @llvm.amdgcn.workitem.id.x()
6+
declare i32 @llvm.amdgcn.workitem.id.y()
7+
declare i32 @llvm.amdgcn.workitem.id.z()
8+
9+
define amdgpu_ps void @undefined_workitems(ptr %p, ptr %q, ptr %r) {
10+
; SelDAG-LABEL: name: undefined_workitems
11+
; SelDAG: bb.0 (%ir-block.0):
12+
; SelDAG-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
13+
; SelDAG-NEXT: {{ $}}
14+
; SelDAG-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr5
15+
; SelDAG-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr4
16+
; SelDAG-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
17+
; SelDAG-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2
18+
; SelDAG-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr1
19+
; SelDAG-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr0
20+
; SelDAG-NEXT: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
21+
; SelDAG-NEXT: [[DEF1:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
22+
; SelDAG-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY]], %subreg.sub1
23+
; SelDAG-NEXT: [[DEF2:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
24+
; SelDAG-NEXT: [[DEF3:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
25+
; SelDAG-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1
26+
; SelDAG-NEXT: [[DEF4:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
27+
; SelDAG-NEXT: [[DEF5:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
28+
; SelDAG-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY4]], %subreg.sub1
29+
; SelDAG-NEXT: [[DEF6:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
30+
; SelDAG-NEXT: [[DEF7:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
31+
; SelDAG-NEXT: [[DEF8:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
32+
; SelDAG-NEXT: S_ENDPGM 0
33+
;
34+
; GlobalISel-LABEL: name: undefined_workitems
35+
; GlobalISel: bb.1 (%ir-block.0):
36+
; GlobalISel-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
37+
; GlobalISel-NEXT: {{ $}}
38+
; GlobalISel-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
39+
; GlobalISel-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
40+
; GlobalISel-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
41+
; GlobalISel-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
42+
; GlobalISel-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
43+
; GlobalISel-NEXT: [[MV1:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
44+
; GlobalISel-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
45+
; GlobalISel-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
46+
; GlobalISel-NEXT: [[MV2:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)
47+
; GlobalISel-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
48+
; GlobalISel-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
49+
; GlobalISel-NEXT: G_STORE [[COPY6]](s32), [[MV]](p0) :: (store (s32) into %ir.p)
50+
; GlobalISel-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
51+
; GlobalISel-NEXT: G_STORE [[COPY7]](s32), [[MV1]](p0) :: (store (s32) into %ir.q)
52+
; GlobalISel-NEXT: G_STORE [[DEF]](s32), [[MV2]](p0) :: (store (s32) into %ir.r)
53+
; GlobalISel-NEXT: S_ENDPGM 0
54+
%id.x = call i32 @llvm.amdgcn.workitem.id.x()
55+
store i32 %id.x, ptr %p
56+
%id.y = call i32 @llvm.amdgcn.workitem.id.y()
57+
store i32 %id.y, ptr %q
58+
%id.z = call i32 @llvm.amdgcn.workitem.id.z()
59+
store i32 %id.z, ptr %r
60+
ret void
61+
}

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll‎

Lines changed: 0 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,6 @@
55
; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mcpu=tonga -mattr=-flat-for-global < %t.bc | FileCheck -check-prefixes=ALL,MESA3D,UNPACKED %s
66
; RUN: llc -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx90a < %t.bc | FileCheck -check-prefixes=ALL,PACKED-TID %s
77
; RUN: llc -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx1100 -amdgpu-enable-vopd=0 < %t.bc | FileCheck -check-prefixes=ALL,PACKED-TID %s
8-
; RUN: llc -mtriple=amdgcn -mcpu=gfx942 -o - %s | FileCheck --check-prefix=UNDEF %s
98

109
declare i32 @llvm.amdgcn.workitem.id.x() #0
1110
declare i32 @llvm.amdgcn.workitem.id.y() #0
@@ -129,30 +128,6 @@ define amdgpu_kernel void @test_reqd_workgroup_size_z_only(ptr %out) !reqd_work_
129128
ret void
130129
}
131130

132-
define amdgpu_kernel void @undefined_workitem_x_only() {
133-
; UNDEF-LABEL: undefined_workitem_x_only:
134-
; UNDEF: ; %bb.0:
135-
; UNDEF-NEXT: s_endpgm
136-
%id.x = call i32 @llvm.amdgcn.workitem.id.x()
137-
ret void
138-
}
139-
140-
define amdgpu_kernel void @undefined_workitem_y_only() {
141-
; UNDEF-LABEL: undefined_workitem_y_only:
142-
; UNDEF: ; %bb.0:
143-
; UNDEF-NEXT: s_endpgm
144-
%id.y = call i32 @llvm.amdgcn.workitem.id.y()
145-
ret void
146-
}
147-
148-
define amdgpu_kernel void @undefined_workitem_z_only() {
149-
; UNDEF-LABEL: undefined_workitem_z_only:
150-
; UNDEF: ; %bb.0:
151-
; UNDEF-NEXT: s_endpgm
152-
%id.z = call i32 @llvm.amdgcn.workitem.id.z()
153-
ret void
154-
}
155-
156131
attributes #0 = { nounwind readnone }
157132
attributes #1 = { nounwind }
158133

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