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fixup! clang-format
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+3
-7
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1 file changed

+3
-7
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llvm/include/llvm/CodeGen/ScheduleDAG.h

Lines changed: 3 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -101,15 +101,13 @@ class TargetRegisterInfo;
101101
SDep() : Dep(nullptr, Data) {}
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103103
/// Constructs an SDep with the specified values.
104-
SDep(SUnit *S, Kind kind, Register Reg)
105-
: Dep(S, kind), Contents() {
104+
SDep(SUnit *S, Kind kind, Register Reg) : Dep(S, kind), Contents() {
106105
switch (kind) {
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default:
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llvm_unreachable("Reg given for non-register dependence!");
109108
case Anti:
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case Output:
111-
assert(Reg &&
112-
"SDep::Anti and SDep::Output must use a non-zero Reg!");
110+
assert(Reg && "SDep::Anti and SDep::Output must use a non-zero Reg!");
113111
Contents.Reg = Reg.id();
114112
Latency = 0;
115113
break;
@@ -208,9 +206,7 @@ class TargetRegisterInfo;
208206
}
209207

210208
/// Tests if this is a Data dependence that is associated with a register.
211-
bool isAssignedRegDep() const {
212-
return getKind() == Data && Contents.Reg;
213-
}
209+
bool isAssignedRegDep() const { return getKind() == Data && Contents.Reg; }
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215211
/// Returns the register associated with this edge. This is only valid on
216212
/// Data, Anti, and Output edges. On Data edges, this value may be zero,

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