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maksleventalmakslevental
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[LLVM][AMDGPU][NFC] clang-format Target/AMDGPU
1 parent 0fdb908 commit 6f1813f

19 files changed

+926
-1371
lines changed

‎llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp‎

Lines changed: 29 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,8 @@
1111
//
1212
// $old = ...
1313
// $dpp_value = V_MOV_B32_dpp $old, $vgpr_to_be_read_from_other_lane,
14-
// dpp_controls..., $row_mask, $bank_mask, $bound_ctrl
14+
// dpp_controls..., $row_mask, $bank_mask,
15+
// $bound_ctrl
1516
// $res = VALU $dpp_value [, src1]
1617
//
1718
// to
@@ -98,8 +99,8 @@ class GCNDPPCombineLegacy : public MachineFunctionPass {
9899
}
99100

100101
MachineFunctionProperties getRequiredProperties() const override {
101-
return MachineFunctionProperties()
102-
.set(MachineFunctionProperties::Property::IsSSA);
102+
return MachineFunctionProperties().set(
103+
MachineFunctionProperties::Property::IsSSA);
103104
}
104105
};
105106

@@ -176,8 +177,9 @@ MachineOperand *GCNDPPCombine::getOldOpndValue(MachineOperand &OldOpnd) const {
176177
if (!Def)
177178
return nullptr;
178179

179-
switch(Def->getOpcode()) {
180-
default: break;
180+
switch (Def->getOpcode()) {
181+
default:
182+
break;
181183
case AMDGPU::IMPLICIT_DEF:
182184
return nullptr;
183185
case AMDGPU::COPY:
@@ -195,7 +197,7 @@ MachineOperand *GCNDPPCombine::getOldOpndValue(MachineOperand &OldOpnd) const {
195197
}
196198

197199
[[maybe_unused]] static unsigned getOperandSize(MachineInstr &MI, unsigned Idx,
198-
MachineRegisterInfo &MRI) {
200+
MachineRegisterInfo &MRI) {
199201
int16_t RegClass = MI.getDesc().operands()[Idx].RegClass;
200202
if (RegClass == -1)
201203
return 0;
@@ -239,9 +241,9 @@ MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI,
239241
TII->isVOPC(OrigOpE32)))) &&
240242
"VOPC cannot form DPP unless mask is full");
241243

242-
auto DPPInst = BuildMI(*OrigMI.getParent(), OrigMI,
243-
OrigMI.getDebugLoc(), TII->get(DPPOp))
244-
.setMIFlags(OrigMI.getFlags());
244+
auto DPPInst = BuildMI(*OrigMI.getParent(), OrigMI, OrigMI.getDebugLoc(),
245+
TII->get(DPPOp))
246+
.setMIFlags(OrigMI.getFlags());
245247

246248
bool Fail = false;
247249
do {
@@ -284,8 +286,8 @@ MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI,
284286

285287
auto *Mod0 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0_modifiers);
286288
if (Mod0) {
287-
assert(NumOperands == AMDGPU::getNamedOperandIdx(DPPOp,
288-
AMDGPU::OpName::src0_modifiers));
289+
assert(NumOperands ==
290+
AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::src0_modifiers));
289291
assert(HasVOP3DPP ||
290292
(0LL == (Mod0->getImm() & ~(SISrcMods::ABS | SISrcMods::NEG))));
291293
DPPInst.addImm(Mod0->getImm());
@@ -308,8 +310,8 @@ MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI,
308310

309311
auto *Mod1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1_modifiers);
310312
if (Mod1) {
311-
assert(NumOperands == AMDGPU::getNamedOperandIdx(DPPOp,
312-
AMDGPU::OpName::src1_modifiers));
313+
assert(NumOperands ==
314+
AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::src1_modifiers));
313315
assert(HasVOP3DPP ||
314316
(0LL == (Mod1->getImm() & ~(SISrcMods::ABS | SISrcMods::NEG))));
315317
DPPInst.addImm(Mod1->getImm());
@@ -440,7 +442,8 @@ MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI,
440442
static bool isIdentityValue(unsigned OrigMIOp, MachineOperand *OldOpnd) {
441443
assert(OldOpnd->isImm());
442444
switch (OrigMIOp) {
443-
default: break;
445+
default:
446+
break;
444447
case AMDGPU::V_ADD_U32_e32:
445448
case AMDGPU::V_ADD_U32_e64:
446449
case AMDGPU::V_ADD_CO_U32_e32:
@@ -561,8 +564,8 @@ bool GCNDPPCombine::combineDPPMov(MachineInstr &MovMI) const {
561564
assert(RowMaskOpnd && RowMaskOpnd->isImm());
562565
auto *BankMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask);
563566
assert(BankMaskOpnd && BankMaskOpnd->isImm());
564-
const bool MaskAllLanes = RowMaskOpnd->getImm() == 0xF &&
565-
BankMaskOpnd->getImm() == 0xF;
567+
const bool MaskAllLanes =
568+
RowMaskOpnd->getImm() == 0xF && BankMaskOpnd->getImm() == 0xF;
566569

567570
auto *BCZOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bound_ctrl);
568571
assert(BCZOpnd && BCZOpnd->isImm());
@@ -577,7 +580,7 @@ bool GCNDPPCombine::combineDPPMov(MachineInstr &MovMI) const {
577580
return false;
578581
}
579582

580-
auto * const OldOpndValue = getOldOpndValue(*OldOpnd);
583+
auto *const OldOpndValue = getOldOpndValue(*OldOpnd);
581584
// OldOpndValue is either undef (IMPLICIT_DEF) or immediate or something else
582585
// We could use: assert(!OldOpndValue || OldOpndValue->isImm())
583586
// but the third option is used to distinguish undef from non-immediate
@@ -601,27 +604,23 @@ bool GCNDPPCombine::combineDPPMov(MachineInstr &MovMI) const {
601604
}
602605
} else if (BoundCtrlZero) {
603606
assert(!MaskAllLanes); // by check [1]
604-
LLVM_DEBUG(dbgs() <<
605-
" failed: old!=0 and bctrl:0 and not all lanes isn't combinable\n");
607+
LLVM_DEBUG(dbgs() << " failed: old!=0 and bctrl:0 and not all lanes "
608+
"isn't combinable\n");
606609
return false;
607610
}
608611
}
609612

610-
LLVM_DEBUG(dbgs() << " old=";
611-
if (!OldOpndValue)
612-
dbgs() << "undef";
613-
else
614-
dbgs() << *OldOpndValue;
615-
dbgs() << ", bound_ctrl=" << CombBCZ << '\n');
613+
LLVM_DEBUG(dbgs() << " old="; if (!OldOpndValue) dbgs() << "undef";
614+
else dbgs() << *OldOpndValue;
615+
dbgs() << ", bound_ctrl=" << CombBCZ << '\n');
616616

617-
SmallVector<MachineInstr*, 4> OrigMIs, DPPMIs;
618-
DenseMap<MachineInstr*, SmallVector<unsigned, 4>> RegSeqWithOpNos;
617+
SmallVector<MachineInstr *, 4> OrigMIs, DPPMIs;
618+
DenseMap<MachineInstr *, SmallVector<unsigned, 4>> RegSeqWithOpNos;
619619
auto CombOldVGPR = getRegSubRegPair(*OldOpnd);
620620
// try to reuse previous old reg if its undefined (IMPLICIT_DEF)
621621
if (CombBCZ && OldOpndValue) { // CombOldVGPR should be undef
622622
const TargetRegisterClass *RC = MRI->getRegClass(DPPMovReg);
623-
CombOldVGPR = RegSubRegPair(
624-
MRI->createVirtualRegister(RC));
623+
CombOldVGPR = RegSubRegPair(MRI->createVirtualRegister(RC));
625624
auto UndefInst = BuildMI(*MovMI.getParent(), MovMI, MovMI.getDebugLoc(),
626625
TII->get(AMDGPU::IMPLICIT_DEF), CombOldVGPR.Reg);
627626
DPPMIs.push_back(UndefInst.getInstr());
@@ -736,7 +735,7 @@ bool GCNDPPCombine::combineDPPMov(MachineInstr &MovMI) const {
736735

737736
Rollback |= !Uses.empty();
738737

739-
for (auto *MI : *(Rollback? &DPPMIs : &OrigMIs))
738+
for (auto *MI : *(Rollback ? &DPPMIs : &OrigMIs))
740739
MI->eraseFromParent();
741740

742741
if (!Rollback) {

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