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Fix ident and features
Add Zimop, remove redundant definition, remove NoSinkSplat.
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2 files changed

+46
-46
lines changed

2 files changed

+46
-46
lines changed

clang/test/Driver/riscv-cpus.c

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@@ -122,6 +122,7 @@
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zihintntl"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zihintpause"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zihpm"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zimop"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zmmul"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zawrs"
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// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zfa"

llvm/lib/Target/RISCV/RISCVProcessors.td

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Original file line numberDiff line numberDiff line change
@@ -408,52 +408,51 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
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[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;
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def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8",
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NoSchedModel,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZifencei,
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FeatureStdExtZicsr,
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FeatureStdExtZicntr,
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FeatureStdExtZihpm,
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FeatureStdExtZihintpause,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC,
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FeatureStdExtV,
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FeatureStdExtZvl256b,
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FeatureStdExtZfh,
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FeatureStdExtZvfh,
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FeatureStdExtZba,
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FeatureStdExtZbb,
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FeatureStdExtZbs,
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FeatureStdExtZicbom,
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FeatureStdExtZicbop,
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FeatureStdExtZicboz,
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FeatureStdExtH,
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FeatureStdExtZihintntl,
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FeatureStdExtZfhmin,
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FeatureStdExtZfa,
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FeatureStdExtZkt,
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FeatureStdExtZcb,
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FeatureStdExtZvbb,
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FeatureStdExtZvbc,
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FeatureStdExtZawrs,
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FeatureStdExtZvkng,
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FeatureStdExtZicond,
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FeatureUnalignedScalarMem,
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FeatureUnalignedVectorMem,
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FeatureStdExtSvnapot,
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FeatureStdExtSvpbmt,
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FeatureStdExtSvinval,
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FeatureStdExtZfbfmin,
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FeatureStdExtZvfbfmin,
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FeatureStdExtZvfbfwma],
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[TuneNoDefaultUnroll,
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TuneOptimizedZeroStrideLoad,
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TuneNoSinkSplatOperands,
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FeaturePostRAScheduler]>;
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NoSchedModel,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZifencei,
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FeatureStdExtZicsr,
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FeatureStdExtZicntr,
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FeatureStdExtZihpm,
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FeatureStdExtZihintpause,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC,
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FeatureStdExtV,
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FeatureStdExtZvl256b,
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FeatureStdExtZfh,
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FeatureStdExtZvfh,
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FeatureStdExtZba,
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FeatureStdExtZbb,
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FeatureStdExtZbs,
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FeatureStdExtZicbom,
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FeatureStdExtZicbop,
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FeatureStdExtZicboz,
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FeatureStdExtZimop,
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FeatureStdExtH,
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FeatureStdExtZihintntl,
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FeatureStdExtZfa,
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FeatureStdExtZkt,
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FeatureStdExtZcb,
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FeatureStdExtZvbb,
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FeatureStdExtZvbc,
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FeatureStdExtZawrs,
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FeatureStdExtZvkng,
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FeatureStdExtZicond,
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FeatureStdExtSvnapot,
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FeatureStdExtSvpbmt,
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FeatureStdExtSvinval,
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FeatureStdExtZfbfmin,
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FeatureStdExtZvfbfmin,
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FeatureStdExtZvfbfwma,
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FeatureUnalignedScalarMem,
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FeatureUnalignedVectorMem],
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[TuneNoDefaultUnroll,
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TuneOptimizedZeroStrideLoad,
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FeaturePostRAScheduler]>;
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def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
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NoSchedModel,

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