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lines changed Original file line number Diff line number Diff line change 122122// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zihintntl"
123123// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zihintpause"
124124// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zihpm"
125+ // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zimop"
125126// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zmmul"
126127// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zawrs"
127128// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zfa"
Original file line number Diff line number Diff line change @@ -408,52 +408,51 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
408408 [TuneNoDefaultUnroll, FeaturePostRAScheduler]>;
409409
410410def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8",
411- NoSchedModel,
412- [Feature64Bit,
413- FeatureStdExtI,
414- FeatureStdExtZifencei,
415- FeatureStdExtZicsr,
416- FeatureStdExtZicntr,
417- FeatureStdExtZihpm,
418- FeatureStdExtZihintpause,
419- FeatureStdExtM,
420- FeatureStdExtA,
421- FeatureStdExtF,
422- FeatureStdExtD,
423- FeatureStdExtC,
424- FeatureStdExtV,
425- FeatureStdExtZvl256b,
426- FeatureStdExtZfh,
427- FeatureStdExtZvfh,
428- FeatureStdExtZba,
429- FeatureStdExtZbb,
430- FeatureStdExtZbs,
431- FeatureStdExtZicbom,
432- FeatureStdExtZicbop,
433- FeatureStdExtZicboz,
434- FeatureStdExtH,
435- FeatureStdExtZihintntl,
436- FeatureStdExtZfhmin,
437- FeatureStdExtZfa,
438- FeatureStdExtZkt,
439- FeatureStdExtZcb,
440- FeatureStdExtZvbb,
441- FeatureStdExtZvbc,
442- FeatureStdExtZawrs,
443- FeatureStdExtZvkng,
444- FeatureStdExtZicond,
445- FeatureUnalignedScalarMem,
446- FeatureUnalignedVectorMem,
447- FeatureStdExtSvnapot,
448- FeatureStdExtSvpbmt,
449- FeatureStdExtSvinval,
450- FeatureStdExtZfbfmin,
451- FeatureStdExtZvfbfmin,
452- FeatureStdExtZvfbfwma],
453- [TuneNoDefaultUnroll,
454- TuneOptimizedZeroStrideLoad,
455- TuneNoSinkSplatOperands,
456- FeaturePostRAScheduler]>;
411+ NoSchedModel,
412+ [Feature64Bit,
413+ FeatureStdExtI,
414+ FeatureStdExtZifencei,
415+ FeatureStdExtZicsr,
416+ FeatureStdExtZicntr,
417+ FeatureStdExtZihpm,
418+ FeatureStdExtZihintpause,
419+ FeatureStdExtM,
420+ FeatureStdExtA,
421+ FeatureStdExtF,
422+ FeatureStdExtD,
423+ FeatureStdExtC,
424+ FeatureStdExtV,
425+ FeatureStdExtZvl256b,
426+ FeatureStdExtZfh,
427+ FeatureStdExtZvfh,
428+ FeatureStdExtZba,
429+ FeatureStdExtZbb,
430+ FeatureStdExtZbs,
431+ FeatureStdExtZicbom,
432+ FeatureStdExtZicbop,
433+ FeatureStdExtZicboz,
434+ FeatureStdExtZimop,
435+ FeatureStdExtH,
436+ FeatureStdExtZihintntl,
437+ FeatureStdExtZfa,
438+ FeatureStdExtZkt,
439+ FeatureStdExtZcb,
440+ FeatureStdExtZvbb,
441+ FeatureStdExtZvbc,
442+ FeatureStdExtZawrs,
443+ FeatureStdExtZvkng,
444+ FeatureStdExtZicond,
445+ FeatureStdExtSvnapot,
446+ FeatureStdExtSvpbmt,
447+ FeatureStdExtSvinval,
448+ FeatureStdExtZfbfmin,
449+ FeatureStdExtZvfbfmin,
450+ FeatureStdExtZvfbfwma,
451+ FeatureUnalignedScalarMem,
452+ FeatureUnalignedVectorMem],
453+ [TuneNoDefaultUnroll,
454+ TuneOptimizedZeroStrideLoad,
455+ FeaturePostRAScheduler]>;
457456
458457def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
459458 NoSchedModel,
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